A memory system having a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for controlling the semiconductor storage device is provided. The control section receives a designating signal for designating one area out of the plural areas of the semiconductor storage device and a relative physical address independent by each area and specifies the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address so that the semiconductor storage device is accessed.
1. A memory system comprising:
a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and
a control section for receiving a designating signal for designating one area out of the plural areas of said semiconductor storage device and a relative physical address independent of each of the areas, and specifying the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address, so that said semiconductor storage device is accessed,
wherein, when one area out of the plural areas is designated by the designating signal, said control section becomes able to access only the designated area,
wherein said semiconductor storage device includes first plural areas each of which becomes accessible when it is designated by the designating signal and a second area which becomes accessible when none of the areas is designated by the designating signal, and
wherein, when one area out of the first plural areas is designated by the designating signal, said control section becomes able to access only the designated area, and when none of the areas is designated by the designating signal, said control section becomes able to access only the second area.
2. The memory system according to claim 1 ,
wherein said semiconductor storage device is erasable by each block unit comprising plural nonvolatile memory cells.
3. The memory system according to claim 2 ,
wherein said semiconductor storage device is a flash memory.
4. The memory system according to claim 2 ,
wherein said semiconductor storage device stores a logical address corresponding to the absolute physical address of each block, each of the areas of said semiconductor storage device comprises a group of plural blocks whose absolute physical addresses are consecutive, and the logical address is a logical address independent by each of the areas.
5. The memory system according to claim 1 , further comprising:
an application selection processing section for selecting an application,
wherein applications are stored in the first plural areas respectively, and an application list showing the correlation between the first plural areas and the applications is stored in the second area, and
wherein said control section receives the designating signal and designates an area in which the selected application is stored in accordance with the application list and becomes able to access only the designated area.
6. The memory system according to claim 5 ,
wherein the applications and data handled by the applications are stored in the first plural areas respectively.
7. The memory system according to claim 6 , further comprising:
a download section for downloading the application from the outside and recording the downloaded application in the first area.
8. The memory system according to claim 1 , further comprising:
a conversion processing section for converting a logical address to the relative physical address in accordance with the logical address stored in said semiconductor storage device, and outputting the relative physical address to said control section.
9. A memory system comprising:
a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and
a control section for receiving a designating signal for designating one area out of the plural areas of said semiconductor storage device and a relative physical address independent of each of the areas, and specifying the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address, so that said semiconductor storage device is accessed,
wherein said semiconductor storage device includes first plural areas each of which becomes accessible by the control section when designated by the designating signal and a second area which becomes accessible by the control section when none of the first plural areas is designated by the designating signal.