Methods used to simultaneously perform automated at-speed testing of multiple gigabit per second high serial pin count devices

1. A method for performing automated at-speed testing of a plurality of devices, comprising:

coupling each multiplexer in a set of multiplexers, the set of multiplexers being on a rider board, to a corresponding pin of the plurality of devices, the plurality of devices being on a device under test board;

using multiplexer control signals to provide various signal paths through the rider board between the set of multiplexers and the plurality of devices; and

routing test signals along respective ones of the various signal paths between the rider board and the plurality of devices on the device under test board, the test signals having multiple gigabit per second (MGBPS) baud rates and the test signals being generated in:

(a) an original one of the devices in the plurality of devices,

(b) a testing system, back to the original one of the devices in the plurality of devices, and

(c) an adjacent one of the devices in the plurality of devices.

2. The method of claim 1 , wherein the generating multiplexer control signals step comprises:

generating first signals indicating where the test signals are being transmitted from;

generating second signals indicating where the test signals are being transmitted to; and

generating the multiplexer control signals from the first and second signals.

3. The method of claim 1 , wherein:

the forming various signal paths step includes forming a self loopback testing signal path to and from each of the devices in the plurality of devices using a respective portion of the set of multiplexers; and

the routing includes routing of the MGBPS test signals along the self loopback testing signal path, thereby executing an at-speed self loopback testing operation.

4. The method of claim 1 , wherein:

the forming various signal paths step includes forming a full duplex adjacent core loopback signal path between pairs of adjacent ones of the devices in the plurality of devices in a predetermined direction using a respective portion of the set of multiplexers; and

the routing includes routing of the MGBPS test signals along the full duplex adjacent core loopback signal path, thereby executing an at-speed full duplex adjacent core loopback testing operation.

5. The method of claim 1 , wherein:

the forming various signal paths step includes forming an internal snake up signal path from a highest numbered one of the devices in the plurality of devices to a lowest numbered one of the devices in the plurality of devices using a respective portion of the set of multiplexers; and

the routing includes routing of the MGBPS test signals along the internal snake up signal path, thereby executing an at-speed internal snake up testing operation.

6. The method of claim 1 , wherein:

the forming various signal paths step includes forming an internal snake down signal path from a lowest numbered one of the devices in the plurality of devices to a highest numbered one of the devices in the plurality of devices using a respective portion of the set of multiplexers; and

the routing includes routing of the MGPBS test signals along the internal snake down signal path, thereby executing an at-speed internal snake down testing operation.

7. The method of claim 1 , wherein:

the forming various signal paths step includes forming an external snake up signal path from a highest numbered one of the devices in the plurality of devices to a lowest numbered one of the devices in the plurality of devices using a respective portion of the set of multiplexers; and

the routing includes routing of the MGBPS test signals received from an external signal source along the external snake up signal path, thereby executing an at-speed external snake up testing operation.

8. The method of claim 1 , wherein:

the forming various signal paths step includes forming an external snake down signal path from a lowest numbered one of the devices in the plurality of devices to a highest numbered one of the devices in the plurality of devices using a respective portion of the set of multiplexers; and

the routing includes routing of the MGBPS test signals received from an external signal source along the external snake down signal path, thereby executing an at-speed external snake down testing operation.

9. The method of claim 1 , further comprising:

multiplexing the test signals from the set of multiplexers to a first bit error rate tester in the testing system; and

multiplexing the test signals from the set of multiplexers to a second bit error rate tester in the testing system;

wherein the forming various signal paths step includes forming a bit error rate testing signal path to and from each of the devices in the plurality of devices using a respective portion of the set of multiplexers;

wherein the routing step routes the MGBPS test signals along the bit error rate testing signal path between individual ones of the devices in the plurality of devices and a respective one of the first and second bit error rate testers.

10. The method of claim 1 , further comprising:

multiplexing the test signals from the set of multiplexers through a first analog tester multiplexer to an analog tester in the testing system; and

multiplexing the test signals from the set of multiplexers through a second analog tester multiplexer to the analog tester in the testing system;

wherein the various signal paths step includes forming an analog testing signal path to and from each of the devices in the plurality of devices using a respective portion of the set of multiplexers;

wherein the routing step individually and simultaneously routes the MGBPS test signals along the analog testing signal path between the devices in the plurality of devices and the analog tester.

11. The method of claim 10 , further comprising:

performing transmit analog testing.

12. The method of claim 10 , further comprising: performing analog receive testing.