IP Library Granted Patent US 6,977,447
Granted Patent B2
US 6,977,447 · App. 10/207,450 · Granted Dec 20, 2005

Method and apparatus for regulating multiple outputs of a single inductor DC to DC converter

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Quick Facts
Patent No.
US 6,977,447
App. No.
10/207,450
Granted
Dec 20, 2005
Kind
B2
Abstract

A method and apparatus for regulating multiple outputs of a single inductor DC to DC converter includes processing that begins by producing a regulation signal to regulate a 1 st output of the multiple outputs based on at least one of the multiple outputs. The processing then continues by identifying one of the multiple outputs to receive energy from the inductor during at least one cycle of the regulation signal. The processing continues by scaling the regulation signal for the at least one cycle based on the voltage of the particular output to receive the energy, the voltage of the 1 st output and the supply voltage to the DC to DC converter when the particular output to receive the energy is not the 1 st output. In this manner, when the output receiving the energy is not the 1 st output (i.e., the directly regulated output), the regulation signal is scaled based on the desired duty cycle for the particular output.

Claims (74)

1. A method for regulating multiple outputs of a single inductor DC to DC converter, the method comprises:

producing a regulation signal to regulate a first output of the multiple outputs based on at least one of the multiple outputs;

identifying one of the multiple outputs to receive energy from the inductor during at least one cycle of the regulation signal;

calculating a calculated duty cycle by dividing a difference between the one of the multiple outputs and the supply voltage by the one of the multiple outputs; and

when the one of the multiple outputs to receive the energy is not the first output, scaling the regulation signal for the at least one cycle based on a scaling factor computed as a ratio between duty cycle of the regulation signal for the first output and the calculated duty cycle.

2. The method of claim 1 further comprises:

when the one of the multiple outputs to receive the energy is the first output, passing the regulation signal without scaling.

3. The method of claim 1 , wherein the scaling the regulation signal further comprises:

computing a second scaling factor for a second one of the multiple outputs based on the second one of the multiple outputs, the first output, and the supply voltage.

4. The method of claim 1 , wherein the identifying the one of the multiple outputs further comprises:

sensing a representative voltage for each of the multiple outputs to produce a plurality of sensed representative voltages; and

comparing the plurality of sensed representative voltages to determine a least favorable comparison; and

identifying the one of the multiple outputs as the one of the multiple outputs that corresponds to the least favorable comparison.

5. An integrated circuit DC-DC converter comprises:

load select module operably coupled to produce a load select signal based on multiple outputs of the integrated circuit DC-DC converter;

feedback module operably coupled to produce a feedback voltage based on the multiple outputs;

regulation module operably coupled to generate a charge signal, a load signal, and a scale enable signal based on the load select signal and the feedback voltage;

scaling module operably coupled to scale the charge signal when the scale enable signal is in a first state to produce a scaled charge signal and to pass the charge signal when the scale enable signal is in a second state, to calculate a calculated duty cycle by dividing a difference between the one of the multiple outputs and the supply voltage by the one of the multiple outputs, to compute a scaling factor as a ratio between duty cycle of the charge signal for the first output and the calculated duty cycle, and to scale the charge signal based on the scaling factor; and

switching module operably coupled to single off-chip inductor, to a first off-chip load, to a second off-chip load, and to a supply voltage, wherein the switching module provides coupling between the single off-chip inductor, the first off-chip load, the second off-chip load, and the supply voltage to produce the multiple outputs.

6. The integrated circuit DC-DC converter of claim 5 further comprises:

the regulation module to generate the charge signal, the load signal, and the scale enable signal such that the switching module provides coupling between the single off-chip inductor, the first off-chip load, the second off-chip load, and the supply voltage to produce the boost-mode multiple outputs and the multiple outputs.

7. The integrated circuit DC-DC converter of claim 5 further comprises:

the regulation module to generate the charge signal, the load signal, and the scale enable signal such that the switching module provides coupling between the single off-chip inductor, the first off-chip load, the second off-chip load, and the supply voltage to produce the buck-mode multiple outputs and the multiple outputs.

8. The integrated circuit DC-DC converter of claim 5 further comprises:

the regulation module operably coupled to:

produce the charge signal to regulate a first output of the multiple outputs from the feedback voltage;

identify one of the multiple outputs to receive energy from the off-chip inductor when the load signal is enabled based on the load select signal; and

when the one of the multiple outputs to receive the energy is not the first output, generate the scale enable signal to be in the first state.

9. The integrated circuit DC-DC converter of claim 5 further comprises:

the regulation module operably coupled to:

when the one of the multiple outputs to receive the energy is the first output, generate the scale enable signal to be in the second state.

10. The integrated circuit DC-DC converter of claim 5 further comprises:

the switching module operably coupled to a third off-chip load to produce a third output of the multiple outputs; and

the scaling module operably coupled to scale the charge signal based a second scaling factor when the scale enable signal is in a third state.

11. An apparatus for regulating multiple outputs from a single inductor DC to DC converter, the apparatus comprises:

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to:

produce a regulation signal to regulate a first output of the multiple outputs based on at least one of the multiple outputs;

identify one of the multiple outputs to receive energy from the inductor during at least one cycle of the regulation signal; and

calculating a calculated duty cycle by dividing a difference between the one of the multiple outputs and the supply voltage by the one of the multiple outputs; and

when the one of the multiple outputs to receive the energy is not the first output, scaling the regulation signal for the at least one cycle based on a scaling factor computed as a ratio between duty cycle of the regulation signal for the first output and the calculated duty cycle.

12. The apparatus of claim 11 , wherein the memory further comprises operational instructions that cause the processing module to:

when the one of the multiple outputs to receive the energy is the first output, pass the regulation signal without scaling.

13. The apparatus of claim 11 , wherein the memory further comprises operational instructions that cause the processing module to scale the regulation signal by:

computing a second scaling factor for a second one of the multiple outputs based on the second one of the multiple outputs, the first output, and the supply voltage.

14. The apparatus of claim 11 , wherein the memory further comprises operational instructions that cause the processing module to identify the one of the multiple outputs by:

sensing a representative voltage for each of the multiple outputs to produce a plurality of sensed representative voltages; and

comparing the plurality of sensed representative voltages to determine a least favorable comparison; and

identifying the one of the multiple outputs as the one of the multiple outputs that corresponds to the least favorable comparison.

15. An integrated circuit comprises:

processing core;

memory operably coupled to the processing core, wherein the memory stores algorithms executed by the processing core;

circuitry module operable to process input signals and output signals; and

DC-DC converter operably coupled to supply voltages to the processing core, the memory and the circuitry module, wherein the DC-DC converter includes:

load select module operably coupled to produce a load select signal based on multiple outputs of the integrated circuit DC-DC converter;

feedback module operably coupled to produce a feedback voltage based on the multiple outputs;

regulation module operably coupled to generate a charge signal, a load signal, and a scale enable signal based on the load select signal and the feedback voltage;

scaling module operably coupled to scale the charge signal when the scale enable signal is in a first state to produce a scaled charge signal and to pass the charge signal when the scale enable signal is in a second state, to calculate a calculated duty cycle by dividing a difference between the one of the multiple outputs and the supply voltage by the one of the multiple outputs, to compute a scaling factor as a ratio between duty cycle of the charge signal for the first output and the calculated duty cycle, and to scale the charge signal based on the scaling factor; and

switching module operably coupled to single off-chip inductor, to a first off-chip load, to a second off-chip load, and to a supply voltage, wherein the switching module provides coupling between the single off-chip inductor, the first off-chip load, the second off-chip load, and the supply voltage to produce the multiple outputs.

16. The integrated circuit of claim 15 further comprises:

the regulation module to generate the charge signal, the load signal, and the scale enable signal such that the switching module provides coupling between the single off-chip inductor, the first off-chip load, the second off-chip load, and the supply voltage to produce the boost-mode multiple outputs and the multiple outputs.

17. The integrated circuit of claim 15 further comprises:

the regulation module to generate the charge signal, the load signal, and the scale enable signal such that the switching module provides coupling between the single off-chip inductor, the first off-chip load, the second off-chip load, and the supply voltage to produce the buck-mode multiple outputs and the multiple outputs.

18. The integrated circuit of claim 15 further comprises:

the regulation module operably coupled to:

produce the charge signal to regulate a first output of the multiple outputs from the feedback voltage;

identify one of the multiple outputs to receive energy from the off-chip inductor when the load signal is enabled based on the load select signal; and

when the one of the multiple outputs to receive the energy is not the first output, generate the scale enable signal to be in the first state.

19. The integrated circuit of claim 15 further comprises:

the regulation module operably coupled to:

when the one of the multiple outputs to receive the energy is the first output, generate the scale enable signal to be in the second state.

20. The integrated circuit of claim 15 further comprises:

the switching module operably coupled to a third off-chip load to produce a third output of the multiple outputs; and

the scaling module operably coupled to scale the charge signal based a second scaling factor when the scale enable signal is in a third state.

Assignments (13)
CHANGE OF NAME Recorded Aug 31, 2017
From: SIGMATEL, INC.
To: SIGMATEL, LLC
Reel/Frame 043735/0306 →
MERGER Recorded Jul 26, 2017
From: SIGMATEL, LLC
To: NXP USA, INC.
Reel/Frame 043328/0351 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
SECURITY AGREEMENT Recorded Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →
SECURITY AGREEMENT Recorded Jun 17, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030628/0636 →
SECURITY AGREEMENT Recorded May 10, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024358/0439 →
SECURITY AGREEMENT Recorded Mar 16, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A.
Reel/Frame 024079/0406 →
SECURITY AGREEMENT Recorded Jul 9, 2008
From: SIGMATEL, INC.
To: CITIBANK, N.A.
Reel/Frame 021212/0372 →
SECURITY AGREEMENT Recorded Mar 8, 2004
From: SIGMATEL, INC.
To: SILICON VALLEY BANK
Reel/Frame 015074/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2002
From: MAY, MARCUS W.
To: SIGMATEL, INC.
Reel/Frame 013160/0026 →