Method and system for using machine-architecture support to distinguish function and routine return values
View Patent ↗A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.
1. A method for automated detection of a failure-to-check-a-return-value error in a computer program, the method comprising:
identifying a machine-architecture feature that can flag a register to indicate a special state of the register so that a subsequent access of the register can be automatically detected by a processor;
identifying a register in which a return value is stored for subsequent access; and
when storing a distinguished value in the register as a return value, employing the machine-architecture feature to flag the register as containing the distinguished value.
2. The method of claim 1 wherein the machine-architecture feature comprises machine support for control speculation of load instructions.
3. The method of claim 2 wherein the machine support for control speculation of load instructions includes special registers associated with general registers.
4. The method of claim 3 wherein, when a special register is set, the special register indicates that a deferred exception has arisen during execution of a speculative load instruction for which the general register corresponding to the special register was specified as the target.
5. The method of claim 1 wherein the register in which a return value is stored may include:
a register in which a function stores a return value;
a register in which a function stores a new value for a variable supplied as a variable argument to the function;
a register in which a routine stores a return value; and
a register in which a routine stores a new value for a variable supplied as a variable argument to the function.
6. The method of claim 1 wherein a distinguished value further includes a value indicating an error condition or another special condition that should not be used for subsequent processing in the way that a non-error or non-special value is used.
7. The method of claim 6 wherein employing the machine-architecture feature to flag the register as containing the distinguished value further includes:
using the register in a way to invoke setting of a special register that flags the register as being in a special state.
8. The method of claim 7 wherein the special register is a special register set to indicate deferral of an exception during processing of a control-speculative instruction.
9. Computer instructions that implement the method of claim 1 stored in a computer-readable medium, including:
an electronic memory;
a mass storage device; and
a removable storage device.
10. A computer system that automatically detects a failure-to-check-a-return-value error in a computer program, the computer system comprising:
a processor that includes a machine-architecture feature that can flag a register to indicate a special state of the register so that a subsequent access of the register can be automatically detected by the processor;
a register in which a return value is stored for subsequent access; and
a stored program that includes a called, executable block of instructions that, when storing a distinguished value in the register as a return value, direct the machine-architecture feature to flag the register as containing the distinguished value.
11. The system of claim 10 wherein the machine-architecture feature comprises machine support for control speculation of load instructions.
12. The system of claim 11 wherein the machine support for control speculation of load instructions includes special registers associated with general registers.
13. The system of claim 12 wherein, when a special register is set, the special register indicates that a deferred exception has arisen during execution of a speculative load instruction for which the general register corresponding to the special register was specified as the target.
14. The system of claim 13 wherein the register in which a return value is stored may include:
a register in which a function stores a return value;
a register in which a function stores a new value for a variable supplied as a variable argument to the function;
a register in which a routine stores a return value; and
a register in which a routine stores a new value for a variable supplied as a variable argument to the function.
15. The system of claim 10 wherein a distinguished value further includes a value indicating an error condition or another special condition that should not be used for subsequent processing in the way that a non-error or non-special value is used.
16. The system of claim 15 wherein directing the machine-architecture feature to flag the register as containing the distinguished value further includes:
using the register in a way to invoke setting, by the processor, of a special register that flags the register as being in a special state.
17. The method of claim 16 wherein the special register is a special register set to indicate deferral of an exception during processing of a control-speculative instruction.