Method for transforming behavioral architectural and verification specifications into cycle-based compliant specifications

1. A method for transforming a behavioral specification of a circuit, comprising:

converting the behavioral specification into a diagram representation, wherein each statement in the behavioral specification is represented in the diagram representation by at least one selected from the group consisting of a node, a decision box, and a connection;

converting a delay from the diagram representation if the behavioral specification comprises a delay, wherein the delay is a delay statement in the behavioral specification;

generating a compliant cycle diagram from the diagram representation;

storing the compliant cycle diagram on tangible memory;

deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

2. The method of claim 1 , further comprising:

verifying the cycle equivalent behavioral specification using a cycle-based simulation system.

3. The method of claim 2 , further comprising:

generating a cycle-based compliant circuit design using the cycle equivalent behavioral specification, if verified.

4. The method of claim 1 , wherein the behavioral specification comprises multiple cycles within a procedural block.

5. The method of claim 1 , wherein the behavioral specification comprises multiple cycles within an initial block.

6. The method of claim 1 , wherein the behavioral specification comprises a cycle delay.

7. The method of claim 1 , wherein converting the delay comprises converting the delay to an equivalent number of clock cycles.

8. A computer system to transform a behavioral specification of a circuit, comprising:

a processor;

a memory; and

software instructions stored in the memory for enabling the computer system under control of the processor, to perform:

converting the behavioral specification into a diagram representation, wherein each statement in the behavioral specification is represented in the diagram representation by at least one selected from the group consisting of a node, a decision box, and a connection;

converting a delay from the diagram representation if the behavioral specification comprises a delay, wherein the delay is a delay statement in the behavioral specification;

generating a compliant cycle diagram from the diagram representation; and deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

9. The computer system of claim 8 , wherein the behavioral specification comprises multiple cycles within a procedural block.

10. The computer system of claim 8 , wherein the behavioral specification comprises multiple cycles within an initial block.

11. The computer system of claim 8 , wherein the behavioral specification comprises a cycle delay.

12. The computer system of claim 8 , wherein converting the delay comprises converting the delay to an equivalent number of clock cycles.

13. A computer-readable medium having recorded thereon a plurality of instructions executable by a processor, comprising the plurality of instructions for transforming a behavioral specification of a circuit by:

converting the behavioral specification into a diagram representation, wherein each statement in the behavioral specification is represented in the diagram representation by at least one selected from the group consisting of a node, a decision box, and a connection;

converting a delay from the diagram representation if the behavioral specification comprises a delay, wherein the delay is a delay statement in the behavioral specification;

generating a compliant cycle diagram from the diagram representation; storing the compliant cycle diagram on tangible memory;

deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

14. The computer-readable medium of claim 13 , wherein the behavioral specification comprises multiple cycle within a procedural block.

15. The computer-readable medium of claim 13 , wherein the behavioral specification comprises multiple cycles within an initial block.

16. The computer-readable medium of claim 13 , wherein the behavioral specification comprises a cycle delay.

17. The computer-readable medium of claim 13 , wherein converting the delay comprises converting the delay to an equivalent number of clock cycles.

18. An apparatus for transforming a behavioral specification of a circuit, comprising:

means for converting the behavioral specification into a diagram representation, wherein each statement in the behavioral specification is represented in the diagram representation by at least one selected from the group consisting of a node, a decision box, and a connection;

means for converting a delay from the diagram representation if the behavioral specification comprises a delay, wherein the delay is a delay statement in the behavioral specification;

means for generating a compliant cycle diagram from the diagram representation; and

means for deriving a cycle equivalent behavioral specification from the compliant cycle diagram.