IP Library › Granted Patent US 6,839,791
Granted Patent B2
US 6,839,791 · App. 10/214,285 · Granted Jan 4, 2005

Method and apparatus for accelerating detection of serial bus device speed signals

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,839,791
App. No.
10/214,285
Granted
Jan 4, 2005
Kind
B2
Abstract

A method and apparatus for accelerating detection of speed code signals, and in particular S 400 signals, for IEEE Standard 1394-1995 serial bus devices. The present invention validates S 400 mode immediately after detecting an S 400 speed signal, or immediately after detecting an S 400 speed signal following a first to S 200 speed signal. The invention further provides S 200 and S 100 mode validation according to current implementations. Additionally, the invention does not require RX_DATA_PREFIX as a pre-requisite for signal detection.

Claims (14)

1. A method of administering a serial bus, the method comprising the acts of:

providing a speed signal register;

detecting a first speed signal received by the speed signal register, the first speed signal indicating a first speed code;

detecting a second speed signal received by the speed signal register, the second speed signal indicating a second speed code, the second speed code being different from the first speed code; and

validating a speed mode based on the order in which the speed signals were received.

2. The method of claim 1 , wherein the first speed signal is a S 200 signal and the second speed signal is an S 400 signal, and the speed mode validated is an S 400 speed mode.

3. The method of claim 1 , further comprising clearing the speed signal register after transmission of a plurality of packets has concluded.

4. The method of claim 1 , further comprising clearing the speed signal register after a chip reset has occurred.

5. The method of claim 1 , further comprising clearing the speed signal register after a self-ID speed signal trap has occurred.

6. A computer-readable medium containing instructions, which, when executed by a computer, administer a serial bus by:

communicating with a speed signal register;

detecting a first speed signal received by the speed signal register, the first speed signal indicating a first speed code;

detecting a second speed signal received by the speed signal register, the second speed signal indicating a second speed code, the second speed code being different from the first speed code; and

validating a speed mode based on the order in which the speed signals were received.

Assignments (1)
CHANGE OF NAME Recorded Jun 13, 2007
From: APPLE COMPUTER, INC.
To: APPLE INC.
Reel/Frame 019668/0117 →