Clock balanced segmentation digital filter provided with optimun area of data path
View Patent ↗The present invention generally relates to provide a clock balanced segmentation digital filter, which is provided with an optimum area of a data path. The digital filter includes a controlling unit, which is connecting with a register, a multiplexer unit, and an arithmetic and logic unit. The present invention utilizes the controlling unit to initialize the filter parameter stored in the register and to segment the whole logic operation procedure to a plurality of operation steps and to arrange the operation procedure. The multiplexer unit is connecting with the register and the arithmetic and logic unit. The multiplexer unit controlled by the controlling unit is choosing the require parameter and data to output into the arithmetic and logic unit to perform the operation. The operation result is stored in the register for using as the following operation parameter. The present is provided with advantages of scaling down the area of logic circuit, low power consumption and rapid operation.
1. A clock balanced segmentation digital filter which is provided with an optimum area of a data path, said digital filter comprising:
a register for storing a plurality of operational parameters;
a single multiplexer unit having a first input coupled to an output of said register;
a single arithmetic and logic unit having an input coupled to an output of said multiplexer unit and an output coupled to said register for storing a current arithmetic operation result thereof in said register as a new operational parameter; and,
a controlling unit coupled to said register and storing an initial filter parameter therein, said controlling unit being coupled to said multiplexer unit and said arithmetic and logic unit for segmenting a required operation procedure into a plurality of sequential operation steps;
wherein said arithmetic logic unit includes a shifter and an adder-subtracter, said shifter having one input coupled to said output of said multiplexer unit for receiving a data signal therefrom and another input coupled to an output of said controlling unit for receiving a bit shift control signal for controlling the number of bits of the data signal that are to be shifted, said shifter having an output coupled to said register for storing said bit shifted data signal therein, said adder-subtracter having a pair of first inputs coupled to said multiplexer unit for receiving data including said initial filter parameter to be combined by one of an addition or subtraction operation and a second input coupled to said controlling unit for receiving a control signal therefrom for controlling addition and subtraction operations thereof, said adder-subtracter having an output coupled to said register for storing said current arithmetic operation result.