IP Library › Granted Patent US 6,944,811
Granted Patent B2
US 6,944,811 · App. 10/215,133 · Granted Sep 13, 2005

Blockage aware zero skew clock routing method

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Quick Facts
Patent No.
US 6,944,811
App. No.
10/215,133
Granted
Sep 13, 2005
Kind
B2
Abstract

A blockage aware zero skew clock routing method for calculating the distance, and therefore the delay, between two points takes into account any blockages along the path between the two points and therefore creates a more usable and realistic measure of delay and allows for minimization, or elimination, of clock skew in the system being designed using the method of the invention.

Claims (87)

1. A blockage aware zero skew clock routing method for calculating delay between points in an electronic system, the blockage aware zero skew clock routing method comprising:

designating a first point in said electronic system;

designating a second point in said electronic system;

designating a path between said first point and said second point;

checking for blockages on said path between said first point and said second point;

if a blockage exists on said path between said first point and said second point, treating said path as an exception;

if no blockage exists on said path between said first point and said second point, calculating a raw distance between said first point and said second point; and

if no blockage exists on said path between said first point and said second point using said raw distance to estimate a signal propagation delay between said first point and said second point.

2. The blockage aware zero skew clock routing method of claim 1 ; wherein,

said electronic system is a microprocessor.

3. The blockage aware zero skew clock routing method of claim 2 ; wherein,

said first point is a clock-in pin on said microprocessor for receiving a clock signal.

4. A blockage aware zero skew clock routing method for calculating delay between points in an electronic system, the blockage aware zero skew clock routing method comprising:

designating a first point in said electronic system;

designating a second point in said electronic system;

designating a path between said first point and said second point;

calculating a raw distance between said first point and said second point on said path;

estimating a signal propagation delay between said first point and said second point using said raw calculated distance between said first point and said second point;

checking for blockages on said path between said first point and said second point; and

if a blockage exists on said path between said first point and said second point, treating said path as an exception.

5. The blockage aware zero skew clock routing method of claim 4 ; wherein,

said electronic system is a microprocessor.

6. The blockage aware zero skew clock routing method of claim 5 ; wherein,

said first point is a clock-in pin on said microprocessor for receiving a clock signal.

7. A blockage aware zero skew clock routing method for calculating delay between points in an electronic system, the blockage aware zero skew clock routing method comprising:

designating a first point in said electronic system;

designating a second point in said electronic system;

designating a path between said first point and said second point;

calculating a raw distance on said path between said first point and said second point;

checking for blockages on said path between said first point and said second point;

if a blockage exists on said path between said first point and said second point, treating said path with an exception routine, said exception routine comprising;

designating a by-pass path around said blockage;

calculating a length of said by-pass path;

adding said calculated length of said by-pass path to said raw distance between said first point and said second point to obtain an effective distance between said first point and said second point; and

estimating a signal propagation delay between said first point and said second point using said effective distance between said first point and said second point; and

if no blockage exists on said path between said first point and said second point using said raw distance to estimate a signal propagation delay between said first point and said second point.

8. The blockage aware zero skew clock routing method of claim 7 ; wherein,

said electronic system is a microprocessor.

9. The blockage aware zero skew clock routing method of claim 8 ; wherein,

said first point is a clock-in pin on said microprocessor for receiving a clock signal.

10. A blockage aware zero skew clock routing method for calculating delay between points in an electronic system, the blockage aware zero skew clock routing method comprising:

designating a first point in said electronic system;

designating a second point in said electronic system;

designating a path between said first point and said second point;

checking for blockages on said path between said first point and said second point;

if a blockage exists on said path between said first point and said second point, treating said path with an exception routine, said exception routine comprising;

calculating a raw distance on said path between said first point and said second point;

designating a by-pass path around said blockage;

calculating a length of said by-pass path;

adding said calculated length of said by-pass path to said raw distance between said first point and said second point to obtain an effective distance between said first point and said second point; and

estimating a signal propagation delay between said first point and said second point using said effective distance between said first point and said second point;

if no blockage exists on said path between said first point and said second point, calculating a raw distance between said first point and said second point; and

if no blockage exists on said path between said first point and said second point using said raw distance to estimate a signal propagation delay between said first point and said second point.

11. The blockage aware zero skew clock routing method of claim 10 ; wherein,

said electronic system is a microprocessor.

12. The blockage aware zero skew clock routing method of claim 11 ; wherein,

said first point is a clock-in pin on said microprocessor for receiving a clock signal.

13. A blockage aware zero skew clock routing method for calculating delay between points in an electronic system, the blockage aware zero skew clock routing method comprising:

designating a first point in said electronic system;

designating a second point in said electronic system;

designating a path between said first point and said second point;

checking for blockages on said path between said first point and said second point;

if a blockage exists on said path between said first point and said second point, treating said path with an exception routine, said exception routine comprising;

designating a by-pass path between said first point and said second point;

calculating a distance between said first point and said second point along said by-pass path; and

estimating a signal propagation delay between said first point and said second point using said calculated distance between said first point and said second point;

if no blockage exists on said path between said first point and said second point, calculating a raw distance between said first point and said second point; and

if no blockage exists on said path between said first point and said second point using said raw distance to estimate a signal propagation delay between said first point and said second point.

14. The blockage aware zero skew clock routing method of claim 13 ; wherein,

said electronic system is a microprocessor.

15. The blockage aware zero skew clock routing method of claim 14 ; wherein,

said first point is a clock-in pin on said microprocessor for receiving a clock signal.

16. A blockage aware zero skew clock routing method for calculating delay between points in an electronic system, the blockage aware zero skew clock routing method comprising:

designating a first point in said electronic system;

designating a second point in said electronic system;

designating a path between said first point and said second point;

calculating a raw distance of said path between said first point and said second point;

checking for blockages on said path between said first point and said second point;

if a blockage exists on said path between said first point and said second point, treating said path with an exception routine, said exception routine comprising;

designating a by-pass path between said first point and said second point;

calculating a distance between said first point and said second point along said by-pass path; and

estimating a signal propagation delay between said first point and said second point using said calculated distance between said first point and said second point on said by-pass path;

if no blockage exists on said path between said first point and said second point using said raw distance to estimate a signal propagation delay between said first point and said second point.

17. The blockage aware zero skew clock routing method of claim 16 ; wherein,

said electronic system is a microprocessor.

18. The blockage aware zero skew clock routing method of claim 17 ; wherein,

said first point is a clock-in pin on said microprocessor for receiving a clock signal.

Assignments (1)
MERGER AND CHANGE OF NAME Recorded Dec 14, 2015
From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.
To: ORACLE AMERICA, INC.
Reel/Frame 037280/0132 →