Apparatus and methods for sharing cache among processors

1. A processing system comprising:

a plurality of processors;

a cache data array;

a crossbar interface connecting the processors with the cache data array;

wherein the cache data array includes a plurality of sub-arrays accessible via a plurality of ports of the crossbar interface; and

a plurality of tag arrays, corresponding to the plurality of processors, respectively, each tag array being arranged so that a location of an entry in an element of the tag array indicates the location of the way where corresponding data is stored in the cache data array and being arranged so that a location of an entry in the element of the tag array further indicates one of the plurality of ports on the crossbar interface via which one of the sub-arrays containing the corresponding data is accessible.

2. The processing system of claim 1 further configured to provide parallel access to the cache data array by the plurality of the processors.

3. The processing system of claim 2 wherein the crossbar interface comprises at least one crossbar.

4. The processing system of claim 1 wherein the cache data array comprises a plurality of sub-arrays, each processor tag array mapped to at least one of the sub-arrays.

5. The processing system of claim 4 wherein the sub-arrays comprise different sizes.

6. The processing system of claim 4 wherein a number of the sub-arrays differs from a number of the tag arrays.

7. The processing system of claim 1 wherein the crossbar interface connects the processors with other agents of the processing system.

8. The processing system of claim 7 wherein the crossbar interface connects the cache data array with other agents of the processing system.

9. A processing system comprising:

a plurality of processors;

a plurality of cache data sub-arrays for holding data requested by at least one of the processors from a memory, each cache data sub-array comprising a crossbar port for interfacing with the processors;

a crossbar having a plurality of ports, via which the processors are linked with the cache data sub-arrays; and

a tag array corresponding to the plurality of processors, respectively, each tag array being arranged so that a location of an element of the tag array indicates the location of the way where corresponding data is stored in one of the plurality of cache data arrays and further being arranged so that a location of an entry in the element of the tag array further indicates by which one of the plurality of ports the indicated one of plurality of cache data sub-arrays is accessible.

10. The processing system of claim 9 wherein each processor is configured to access one of the cache data sub-arrays at the same time that another processor accesses another of the cache data sub-arrays.

11. A method for retrieving a data line from a cache data array holding at least one line of data requested by at least one of a plurality of processors from a memory, said method comprising the steps of:

searching a tag array for a tag reference for the data line, said step performed by a requesting processor;

locating the data line among a plurality of sub-arrays in the cache data array based upon the location in the tag array of the tag reference;

identifying one of a plurality or ports via which the sub-array holding the data line is accessible by the requesting processor; and

delivering the located data line to the requesting processor.

12. The method of claim 11 wherein the locating and delivering steps are performed via a crossbar interface.

13. The method of claim 11 wherein the searching step is performed by the requesting processor using a tag array dedicated to the requesting processor.

14. The method of claim 13 further comprising the step of updating the tag array of the requesting processor to refer to the retrieved data line.

15. The method of claim 11 wherein the locating step is performed in one of a plurality of sub-arrays of the cache data array, via one of a plurality of crossbar ports corresponding to the sub-arrays.

16. The method of claim 15 wherein the tag array includes an element for each line of data in the cache data array, said method further comprising the step of associating a tag array element with a sub-array.

17. The method of claim 15 wherein the locating step is performed using an indication of a way where a data line is stored.

18. The method of claim 11 wherein the delivering step comprises the steps of:

victimizing a processor to allocate a way where the data line is to be stored in the cache data array;

retrieving the data line from the memory; and

storing the retrieved data line in the cache data array.

19. The method of claim 11 wherein the delivering step comprises the step of using an occupancy vector for a processor tag array to allocate a way where the data line is to be stored in the cache data array.