Clock reconstruction for time division multiplexed traffic transported over asynchronous ethernet networks
View Patent ↗A clock reconstruction mechanism for synchronous TDM communications traffic transported over asynchronous networks such as Ethernet networks. The invention is applicable to edge switches in Metropolitan Area Networks (MANs) that transport legacy TDM traffic using a Circuit Emulation Services (CES) module whereby TDM traffic is encapsulated and transported across the Ethernet network where it is de-encapsulated and clocked out to the destination. The mechanism encapsulates the input TDM data stream into Ethernet packets and inserts a network timestamp within the packet. At the destination CES, a local timestamp is generated for each received packet as it is received. The network timestamp is extracted and input along with the local timestamp to a Digital Time Locked Loop (DTLL) which is operative to accurately reconstruct the original transmit TDM clock. The filter in the DTLL performs a Least Squares Regression (LSR) algorithm and Infinite Impulse Response (IIR) filter algorithm to generate a clock control signal for adjusting the clock generated.
1. A method of clock synchronization for use in transporting synchronous traffic over an asynchronous network, said method comprising the steps of:
extracting a network timestamp from packets transported over said asynchronous network;
generating a local timestamp for each received packet utilizing a local clock source;
fitting a best straight line through sample points of network timestamp data and local timestamp data and generating a clock control signal in accordance with the resulting slope of said line; and
adjusting said local clock source in accordance with said clock control signal so as to generate a reconstructed clock therefrom.
2. The method according to claim 1 , wherein said step of fitting a best straight line is performed to quickly acquire said local reconstructed clock frequency.
3. The method according to claim 2 , wherein said clock control signal increases the frequency of said local clock source if said slope is greater than 45 degrees.
4. The method according to claim 2 , wherein said clock control signal decreases the frequency of said local clock source if said slope is less than 45 degrees.
5. The method according to claim 2 , wherein said slope substantially equal to 45 degrees indicates that the frequency of said local clock source is substantially equal to that of a master clock used to generate said network timestamp.
6. The method according to claim 1 , wherein said network timestamp comprises 32 bits.
7. The method according to claim 1 , wherein said local timestamp comprises 32 bits.
8. The method according to claim 1 , wherein said network timestamp is generated utilizing a 16 MHz clock.
9. The method according to claim 1 , wherein the nominal frequency of said local clock source is 16 MHz.
10. The method according to claim 1 , wherein said asynchronous network comprises an Ethernet network.
11. The method according to claim 1 , wherein said synchronous traffic comprises traffic complying with Time Division Multiplexing (TDM) based T1 or E1 communications standard.
12. The method according to claim 1 , further comprising the step of extracting a sequence number from each received packet for use in handling packets received out of sequence.
13. The method according to claim 1 , wherein the frequency of said local clock source is a multiple of the data rate of said synchronous traffic.
14. The method according to claim 1 , wherein said method implemented in an Application Specific Integrated Circuit (ASIC).
15. The method according to claim 1 , wherein said method implemented in a Field Programmable Gate Array (FPGA).
16. An apparatus for reconstructing a clock for synchronous traffic transported over an asynchronous network, comprising:
means for extracting a network timestamp from packets received over said asynchronous network, said network timestamp generated using a master clock and transported over said asynchronous network;
means for generating a local timestamp for each received packet from utilizing a reconstructed clock generated by a local clock source;
a filter to track differences between said local clock and a master clock used to generate said received network timestamp by fitting a best straight line through sample points of said network timestamp and said local timestamp and generating a clock control signal in accordance with the resulting slope of said line; and
a clock generator comprising said local clock source and to output said reconstructed clock having a frequency determined in accordance with said clock control signal.
17. The apparatus according to claim 16 , wherein said clock control signal filter is generated as a function of the frequency characteristics of said local clock.
18. The apparatus according to claim 16 , wherein said filter quickly acquire said local reconstructed clock frequency.
19. The apparatus according to claim 18 , wherein said filter generates said clock control signal so as to increase the frequency of said local clock source if said slope is greater than 45 degrees.
20. The apparatus according to claim 18 , wherein said filter generates said clock control signal so as to decrease the frequency of said local clock source if said slope is less than 45 degrees.
21. The apparatus according to claim 18 , wherein said slope substantially equal to 45 degrees indicates that the frequency of said local clock source is substantially equal to that of said master clock.
22. The apparatus according to claim 16 , wherein said filter comprises an Infinite Impulse Response (IIR) filter whose input comprises said network timestamp and said local timestamp and whose output comprises an adjustment signal used in generating said clock control signal.
23. The apparatus according to claim 16 , wherein said network timestamp comprises 32 bits.
24. The apparatus according to claim 16 , wherein said local timestamp comprises 32 bits.
25. The apparatus according to claim 16 , wherein said network timestamp is generated utilizing a 16 MHz clock.
26. The apparatus method according to claim 16 , wherein the nominal frequency of said local clock source is 16 MHz.
27. The apparatus according to claim 16 , wherein said asynchronous network comprises an Ethernet network.
28. The apparatus according to claim 16 , wherein said synchronous traffic comprises traffic complying with Time Division Multiplexing (TDM) based T1 or E1 communications standard.
29. The apparatus according to claim 16 , wherein said means for generating a local timestamp, said filter and said clock generator operate as a Time Locked Loop (TLL).
30. The apparatus according to claim 16 , further comprising the step of extracting a sequence number from each received packet for use in handling packets received out of sequence.
31. The apparatus according to claim 16 , wherein the frequency of said local clock source is a multiple of the data rate of said synchronous traffic.
32. The apparatus according to claim 16 , wherein said apparatus implemented in an Application Specific Integrated Circuit (ASIC).
33. The apparatus according to claim 16 , wherein said apparatus implemented in a Field Programmable Gate Array (FPGA).
34. A Circuit Emulation Services (CES) apparatus for transmitting and receiving synchronous TDM traffic over an synchronous Ethernet network, comprising:
a PHY circuit for receiving and transmitting Time Division Multiplexing (TDM) based communications;
an encapsulation module comprising:
means for segmenting received TDM frames into one or more Ethernet packets;
means for generating and inserting a network timestamp in each Ethernet packet before transmission over said Ethernet network;
means for receiving Ethernet packets from said Ethernet network, re-assembling TDM frames and extracting received network timestamps therefrom, said re-assembled TDM frames output utilizing a reconstructed TDM clock;
a clock reconstruction module for generating said reconstructed TDM clock and comprising:
means for generating a local timestamp for each received packet utilizing said reconstructed clock generated by a local clock source;
a filter to track differences between said local clock and a master clock used to generate said received network timestamp by fitting a best straight line through sample points of said network timestamp and said local timestamp and generating a clock control signal in accordance with the resulting slope of said line; and
a clock generator comprising said local clock source, said clock generator for outputting said reconstructed clock having a frequency determined in accordance with said clock control signal.
35. An edge switch, comprising:
a plurality of user ports for interfacing said edge switch to one or more users;
a circuit Emulation Services (CES) module comprising:
a PHY circuit adapted to receive and to transmit Time Division Multiplexing (TDM) based communications;
an encapsulation module comprising means for segmenting received TDM frames into one or more Ethernet packets, means for generating and inserting a network timestamp in each Ethernet packet before transmission over said Ethernet network and means for receiving Ethernet packets from said Ethernet network, re-assembling TDM frames and extracting received network timestamps therefrom, said re-assembled TDM frames output utilizing a reconstructed TDM clock;
a clock reconstruction module for generating said reconstructed TDM clock and comprising means for generating a local timestamp for each received packet utilizing said reconstructed clock generated by a local clock source, a filter for tracking differences between said local clock and a master clock used to generate said received network timestamp by fitting a best straight line through sample points of said network timestamp and said local timestamp and generating a clock control signal in accordance with the resulting slope of said line and a clock generator comprising said local clock source and operative to output said reconstructed clock having a frequency determined in accordance with said clock control signal;
a plurality of network ports for interfacing said edge switch to one or more communication links; and
a packet processor comprising ingress packet processing means and egress packet processing means.
36. A method of clock synchronization for use in transporting synchronous traffic over an asynchronous network, said method comprising the steps of:
extracting a network timestamp from packets transported over said asynchronous network;
generating a local timestamp for each received packet utilizing a local clock source;
applying an Infinite Impulse Response (IIR) filter to network timestamp data and local timestamp data to generate a clock adjustment signal; and
adjusting said local clock source in accordance with said clock adjustment signal so as to generate a reconstructed clock therefrom.
37. A network switch, comprising:
a plurality of user ports for interfacing said edge switch to one or more users;
a Circuit Emulation Services (CES) module comprising:
a PHY circuit to receive and to transmit Time Division Multiplexing (TDM) based communications;
an encapsulation module comprising means for segmenting received TDM frames into one or more Ethernet packets, means for generating and inserting a network timestamp in each Ethernet packet before transmission over said Ethernet network and means for receiving Ethernet packets from said Ethernet network, re-assembling TDM frames and extracting received network timestamps therefrom, said re-assembled TDM frames output utilizing a reconstructed TDM clock;
a clock reconstruction module for generating said reconstructed TDM clock, said clock reconstruction module comprising:
means for extracting a network timestamp from packets transported over said asynchronous network;
means for generating a local timestamp for each received packet utilizing a local clock source;
means for applying an Infinite Impulse Response (IIR) filter to network timestamp data and local timestamp data to generate a clock adjustment signal;
means for adjusting said local clock source in accordance with said clock adjustment signal so as to generate a reconstructed clock therefrom;
a plurality of network ports for interfacing said edge switch to one or more communication links; and
a packet processor comprising ingress packet processing means and egress packet processing means.