IP Library Granted Patent US 6,900,091
Granted Patent B2
US 6,900,091 · App. 10/218,668 · Granted May 31, 2005

Isolated complementary MOS devices in epi-less substrate

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Quick Facts
Patent No.
US 6,900,091
App. No.
10/218,668
Granted
May 31, 2005
Kind
B2
Abstract

An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Claims (9)

1. A process of fabricating a semiconductor device comprising:

providing a semiconductor substrate of a first conductivity type, the substrate not containing an epitaxial layer,

forming a stair-step mask layer on a surface of the substrate, said mask comprising:

a first section having a first thickness, and

second and third sections locate don opposite sides of the first section, the second and third sections having a second thickness greater than the first thickness;

implanting a dopant of a second conductivity type through the mask layer so as to form an isolation region in the substrate, the isolation region isolating an enclosed region of the substrate from a remaining portion of the substrate; and resolving the mask layer.

2. The process of claim 1 wherein the isolation region includes sidewalls, the sidewalls reaching a surface of the substrate in areas below the second and third sections of the mask layer, respectively.

3. The process of claim 1 wherein the enclosed region is located generally directly below the first section of the mask layer.

4. The process of claim 3 wherein the mask layer comprises an oxide.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2025
From: ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 071234/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2007
From: WILLIAMS, RICHARD K
To: ADVANCED ANALOGIC TECHNOLOGIES, INC.
Reel/Frame 019092/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2007
From: CHAN, WAI TIEN
To: ADVANCED ANALOGIC TECHNOLOGIES (HONG KONG) LIMITED
Reel/Frame 019092/0475 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2004
From: CORNELL, MICHAEL E.
To: ADVANCED ANALOGIC TECHNOLOGIES, INC.
Reel/Frame 014927/0127 →