IP Library Granted Patent US 7,222,146
Granted Patent B2
US 7,222,146 · App. 10/222,612 · Granted May 22, 2007

Method and apparatus for facilitating exception-free arithmetic in a computer system

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Quick Facts
Patent No.
US 7,222,146
App. No.
10/222,612
Granted
May 22, 2007
Kind
B2
Abstract

One embodiment of the present invention provides a system that facilitates performing exception-free arithmetic operations within a computer system. During execution of a computer program, the system receives an instruction to perform an arithmetic operation that involves manipulating floating-point values. If the arithmetic operation manipulates a floating-point value representing {+0}, the arithmetic operation is performed in a manner consistent with {+0} representing a set containing a single value “−0”, wherein “−0” is the limit of a sequence of values that approaches zero only from above. Similarly, if the arithmetic operation manipulates a floating-point value representing {−0}, the arithmetic operation is performed in a manner consistent with {−0} representing a set containing a single value “+0”, wherein “+0” is the limit of a sequence of values that approaches zero only from below.

Claims (26)

1. An apparatus that facilitates performing exception-free arithmetic operations within a computer system, comprising:

an arithmetic unit that is configured to receive an instruction to perform an arithmetic operation during execution of a program on the computer system, wherein the arithmetic operation manipulates floating-point values, wherein the arithmetic operation is an interval operation that manipulates at least one interval, and wherein the interval is defined by a first floating-point value that specifies a left endpoint (lower bound) of the interval and a second floating-point value that specifies a right endpoint (upper bound) of the interval; and

wherein in response to the instruction, the arithmetic unit is configured to perform the arithmetic operation;

wherein if the arithmetic operation manipulates a floating-point value representing {+0}, the arithmetic operation is performed in a manner consistent with {+0} representing the limit of a sequence of values that approaches zero only from above; and

wherein if the arithmetic operation manipulates a floating-point value representing {−0}, the arithmetic operation is performed in a manner consistent with {−0} representing the limit of a sequence of values that approaches zero only from below.

2. The apparatus of claim 1 ,

wherein if the arithmetic operation divides a floating-point value less than zero by {−0}, the result of the division is {+4};

wherein if the arithmetic operation divides a floating-point value less than zero by {+0}, the result of the division is {−4};

wherein if the arithmetic operation divides a floating-point value greater than zero by {−0}, the result of the division is {−4}; and

wherein if the arithmetic operation divides a floating-point value greater than zero by {+0}, the result of the division is {+4}.

3. The apparatus of claim 2 ,

wherein if the arithmetic operation divides {−4} by {−4}, {−0} by {−0}, {+0} by {+0} or {+4} by {+4}, the result of the division is the interval [+0, +4]; and

wherein if the arithmetic operation divides {−4} by {−4}, {+0} by {−0}, {−0} by {+0} or {−4} by {+4}, the result of the division is the interval [−4, −0].

4. The apparatus of claim 1 ,

wherein if the arithmetic operation multiplies {−0} by {−4} or {+0} by {+4}, the result of the multiplication is the interval [+0, +4]; and

wherein if the arithmetic operation multiplies {+0} by {−4} or {−0} by {+4}, the result of the multiplication is the interval [−4, −0].

5. The apparatus of claim 4 ,

wherein if the arithmetic operation multiplies {−0} by {−0} or {−0} by a floating-point value, x, wherein −4<x<−0, the result of the multiplication is {+0};

wherein if the arithmetic operation multiplies {−0} by {+0}, {+0} by {−0}, {+0} by a floating-point value, y, +0<y<+4, or {+0} by a floating-point value, y, −4<y<−0, the result of the multiplication is {−0}; and

wherein if the arithmetic operation multiplies {+0} by {+0} or {+0} by a floating-point value, y, wherein +0<y<+4, the result of the multiplication is {+0}.

6. The apparatus of claim 1 ,

wherein if the arithmetic operation adds {−4} and {+4} or {+4} and {−4}, the result of the addition is R*; and

wherein if the arithmetic operation adds {−0} and {+0} or {+0} and {−0}, the result of the addition is the set {−0, +0}=[−0, +0]=0.

7. The apparatus of claim 1 ,

wherein if the arithmetic operation subtracts {−4} and {+4}, the result of the subtraction is R*; and

wherein if the arithmetic operation subtracts {+0} from {+0} or {−0} from {+0}, the result of the subtraction is the set {−0, +0}=[−0, +0]=0.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Dec 16, 2015
From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.
To: ORACLE AMERICA, INC.
Reel/Frame 037302/0772 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2003
From: WALSTER, G. WILLIAM; HANSEN, ELDON R.
To: SUN MICROSYSTEMS, INC.
Reel/Frame 013818/0377 →