Memory system and semiconductor integrated circuit in which operation timings can be set externally
View Patent ↗A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time. When power is turned on, the set data that are stored in the ferroelectric memory are stored and retained in a latch circuit by a control circuit. Based on the set data retained in the latch circuit, data writing is performed in the ferroelectric memory respectively in the power-on state and in the power-off instruction time. Thus, operations of the ferroelectric memory can be controlled with desired operation timings according to operating conditions for each memory system. Excessive stress application to the ferroelectric memory during the power-on state is prevented and endurance deterioration is suppressed, while data retention characteristics after power-off are improved.
1. A memory system comprising:
a non-volatile memory having a plurality of circuit blocks operated by inputting a first signal;
another memory having a plurality of circuit blocks operated by inputting a second signal;
a data latch circuit retaining at least one of output timings and cycles of the first signal and at least one of output timings and cycles of the second signal, wherein said at least one of output timings and cycles of the first signal is diffrent from said at least one of output timings and cycles of the second signal and at least one of output timings and cycles of the first and second signals are adjusted by a first and second variable delay circuit, respectively; and
a timing generating circuit outputting the first signal to the non-volatile memory and outputting the second signal to the other memory according to at least one of the output timings and the cycles of the first signal and the second signal which are retained in the data latch circuit.
2. A memory system comprising:
a non-volatile memory having a plurality of circuit blocks operated by inputting a first signal;
another memory having a plurality of circuit blocks operated by inputting a second signal;
a data latch circuit retaining at least one of output timings and cycles of the first signal and at least one of output timings and cycles of the second signal; and
a timing generating circuit outputting the first signal to the non-volatile memory and outputting the second signal to the other memory according to at least one of the output timings and the cycles of the first signal and the second signal which are retained in the data latch circuit,
wherein:
the non-volatile memory stores the output timings and the cycles of the first signal and output timings and cycles of the second signal beforehand and comprises another timing generating circuit; and
the other timing generating circuit transfers at least one of the output timings and the cycles of the first signal and at least one of the output timings and the cycles of the second signal stored in the non-volatile memory to the data latch circuit when power is turned on.
3. A semiconductor integrated circuit wherein the memory system according to claim 1 is incorporated on a single chip.
4. The memory system according to claim 1 , wherein:
the non-volatile memory stores the output timings and the cycles of the first signal and output timings and cycles of the second signal beforehand and comprises another timing generating circuit; and
the other timing generating circuit transfers at least one of the output timings and the cycles of the first signal and at least one of the output timings and the cycles of the second signal stored in the non-volatile memory to the data latch circuit when power is turned on.
5. A memory system comprising:
a non-volatile memory having a plurality of circuit blocks operated by inputting a first signal;
another memory having a plurality of circuit blocks operated by inputting a second signal;
a data latch circuit retaining at least one of output timings and cycles of the first signal and at least one of output timings and cycles or the second signal; and
a timing generating circuit outputting the first signal to the non-volatile memory and outputting the second signal to the other memory according to at least one of the output tunings and the cycles of the first signal and the second signal which are retained in the data latch circuit, wherein the timing generating circuit comprises firs and second variable delay circuits for adjusting at least one of timings and cycles of the first and second signals respectively according to data retained in the data latch circuit.