Serial interface unit with transmit monitor
View Patent ↗In a serial interface unit ( 10 ) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output ( 24 ) via an output driver ( 22 ). A transmit monitor ( 52 ) compares the data supplied by the data source with the data received at the data output ( 24 ) via the output driver ( 22 ). The transmit monitor outputs an error signal when the data so compared do not coincide.
1. A serial interface unit for the transmission and reception of data comprising:
a data source ( 20 ) supplying serial output data a single bit at a time;
an output driver ( 22 ) having an input ( 1 ) receiving the serial data and an output ( 2 ) supplying a data output line ( 26 ); and
a transmit monitor ( 52 ) connected to the output driver ( 22 ), said transmit monitor ( 52 ) comparing data at said input ( 1 ) of said output driver ( 22 ) and data at said output ( 2 ) of said output driver ( 22 ) and generating an error signal when the compared data do not coincide, said transmit monitor ( 52 ) including
an exclusive-OR circuit ( 58 ) with a first input connected to said input ( 1 ) of said output driver ( 22 ), a second input connected to said output ( 2 ) of said output driver ( 22 ) and an output, and
a D flip-flop ( 62 ) having a D input connected to said output of said exclusive-OR circuit ( 58 ) and an output, said D flip-flop ( 62 ) temporarily storing the output said exclusive-OR circuit ( 58 ).
2. The serial interface unit according to claim 1 , wherein:
said transmit monitor ( 52 ) further includes
a first AND circuit ( 60 ) having a first input connected to said output of said exclusive-OR circuit, a second input and an output connected to said D input of said D flip-flop ( 62 ), said first AND circuit ( 60 ) forming a connection between said output of said exclusive-OR circuit ( 58 ) and said D input of said D flip-flop ( 62 ),
a second AND circuit ( 64 ) having a first input connected to said output of said D flip-flop ( 62 ), a second inverting input receiving a RESET input and an output connected to said second input of said first AND circuit ( 60 );
whereby said D flip-flop ( 62 ) stores said output of said exclusive-OR circuit ( 58 ) until said second inverting input of said second AND circuit ( 64 ) receives said RESET signal.
3. The serial interface unit according to claim 1 , further comprising:
a clock signal input receiving a clock signal supplied to a clock signal line and to said transmit monitor circuit; and
said transmit monitor is responsive to said clock signal for comparing data at said input ( 1 ) of said output driver ( 22 ) and data at said output ( 2 ) of said output driver ( 22 ) at a time relative to said clock signal during which a receive serial interface unit ( 14 ) samples data on said data output line ( 26 ).