Dual-sided capacitor

1. A capacitor comprising:

a dual-sided electrode comprising an oxide layer between two conductive layers, wherein one of said two conductive layers is a doped polycrystalline layer in contact with said oxide layer;

a dielectric layer in contact with both sides of said dual-sided electrode; and

a conductive layer over said dielectric layer.

2. The capacitor of claim 1 , wherein the other one of said two conductive layers is a layer of hemispherical grained polysilicon, said oxide layer being located between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

3. The capacitor of claim 1 , wherein said oxide layer is a native oxide layer.

4. The capacitor of claim 3 , wherein said native oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

5. The capacitor of claim 1 , wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

6. The capacitor of claim 5 , wherein said doped polycrystalline layer is formed of polysilicon.

7. The capacitor of claim 1 , wherein said dual-sided electrode is a lower electrode of said capacitor.

8. The capacitor of claim 1 , wherein said dual-sided electrode is an PH 3 annealed dual-sided electrode.

9. The capacitor of claim 1 , wherein said oxide layer is an ALD oxide layer.

10. The capacitor of claim 1 , wherein said oxide layer is a thermally grown oxide layer.

11. A dual-sided capacitor electrode comprising:

an annealed doped polycrystalline layer having HSG grains of a first thickness;

a layer of hemispherical grained polysilicon having HSG grains of a second thickness; and

an oxide layer between said annealed doped polycrystalline layer and said layer of hemispherical grained polysilicon.

12. The dual-sided capacitor electrode of claim 11 , wherein said oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

13. The dual-sided capacitor electrode of claim 11 , wherein said second thickness is greater than said first thickness.

14. The dual-sided capacitor electrode of claim 11 , wherein said second thickness is of about 100 Angstroms to about 500 Angstroms.

15. The dual-sided capacitor electrode of claim 11 , wherein said first thickness is of about 10 Angstroms to about 50 Arigstroms.

16. The dual-sided capacitor electrode of claim 11 , wherein said dual-sided electrode is a lower electrode of a capacitor.

17. The dual-sided capacitor electrode of claim 11 , wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

18. The dual-sided capacitor electrode of claim 11 , wherein said doped polycrystalline layer is formed of polysiicon.

19. A memory cell comprising:

a transistor; and

a capacitor including a dual-sided electrode comprising a doped polycrystalline layer, a native oxide layer and a layer of hemispherical grained polysilicon, said dual sided electrode being electrically connected to one of a source and drain region of said transistor.

20. The memory cell of claim 19 , wherein said native oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

21. The memory cell of claim 19 , wherein said native oxide layer is formed between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

22. The memory cell of claim 19 , wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

23. The memory cell of claim 19 , wherein said dual-sided electrode is a lower electrode.

24. The memory cell of claim 19 , wherein said native oxide layer is an ALD oxide layer.

25. The memory cell of claim 19 , wherein said native oxide layer is a thermally grown oxide layer.