IP Library › Granted Patent US 6,643,160
Granted Patent Utility
US 6,643,160 · Confirmation No. 5538

DATA BUS ARCHITECTURE FOR INTEGRATED CIRCUIT DEVICES HAVING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH A LARGE ASPECT RATIO PROVIDING REDUCED CAPACITANCE AND POWER REQUIREMENTS

Inventor: Kim Carver Hardee
Patented Case View Patent ↗ View Publication ↗
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 Code Description Pages PDF
2003-09-09 IFEE Issue Fee Payment (PTO-85B) 1 View
2002-10-02 TRNA Transmittal of New Application 2 View
2002-10-02 DRW Drawings-only black and white line drawings 6 View
2002-08-28 TRNA Transmittal of New Application 3 View
2002-08-28 A.PE Preliminary Amendment 4 View
2002-08-28 SPEC Specification 10 View
2002-08-28 CLM Claims 3 View
2002-08-28 ABST Abstract 1 View
2002-08-28 DRW Drawings-only black and white line drawings 6 View
2002-08-28 OATH Oath or Declaration filed 2 View
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Quick Facts
Patent No.
US 6,643,160
App. No.
10/230,239
Filed
2002-08-28
Granted
2003-11-04
Pub. No.
US20030022476A1
Art Unit
2824
PTA
0 days