IP Library Granted Patent US 6,910,103
Granted Patent B2
US 6,910,103 · App. 10/230,702 · Granted Jun 21, 2005

Caching data

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Quick Facts
Patent No.
US 6,910,103
App. No.
10/230,702
Granted
Jun 21, 2005
Kind
B2
Abstract

A method of caching data is provided, which includes a plurality of processes 1602 to 1605 , a cache manager 813 and a data type register 805 including at least one data type 1901 and a corresponding data type bit 1903 . Said data type bit 1903 is set ( 1904 ) within the register 805 on being accessed by each of said processes and subsequently reset ( 1905 ) within the register. The cache manager 813 restores ( 1501 ) each of said set data type bit and identifies its corresponding data type 1901 . The cache manager writes the output data 1609, 1610, 1611 of each of said processes 1603, 1604, 1605 within a memory cache 2001 and said cache manager resets ( 1505 ) said memory cache 2001 when the data type bit set by the last of said processes 1602 is reset.

Claims (38)

1. A method of caching data, said method including a plurality of processes, a cache manager and a data type register including at least one data type and a corresponding data type bit, wherein:

a data type bit is set within said register on being accessed by each of said processes and subsequently reset within said register;

said cache manager restores each of said set data type bit and identifies its corresponding data type;

said cache manager writes the output data of each of said processes within a memory cache; and

said cache manager resets said memory cache when the data type bit set by the last of said processes is reset.

2. A method of caching data according to claim 1 , wherein said plurality of processes comprises application modules, which are initialised.

3. A method of caching data according to claim 2 , wherein each of said application modules defines a functionality of an application.

4. A method of caching data according to claim 2 , wherein said data type register, including at least said one data type and corresponding data type bit is generated by said initialisation of said processes.

5. A method of caching data according to claim 2 , wherein said application module initialisation takes place at the start of said application.

6. A method of caching data according to claim 2 , wherein said application module initialisation takes after said start of said application.

7. An apparatus configured to cache data, comprising display means, storage means and processing means, wherein:

said display means is configured to display a plurality of processes;

said storage means is configured to store said plurality of processes, a cache manager and a data type register including at least one data type and a corresponding data type bit; and

said processing means is configured by said cache manager to perform the processing steps of:

setting a data type bit within said register on being accessed by each of said processes and subsequently resetting said data type bit within said register;

restoring each of said set data type bit and identifying its corresponding data type;

storing the output data of each of said processes within a memory cache; and

resetting said memory cache when the data type bit set by the last of said processes is reset.

8. An apparatus for caching data according to claim 7 , wherein said plurality of processes comprises application modules, which are initialised.

9. An apparatus for caching data according to claim 8 , wherein each of said application modules defines a functionality of an application.

10. An apparatus for caching data according to claim 8 , wherein said data type register, including at least said one data type and corresponding data type bit is generated by said initialisation of said processes.

11. An apparatus for caching data according to claim 8 , wherein said application module initialisation takes place at the start of said application.

12. An apparatus for caching data according to claim 8 , wherein said application module initialisation takes after said start of said application.

13. A computer system programmed to cache data, including a plurality of processes, a cache manager and a data type register including at least one data type and a corresponding data type bit, programmed to perform the processing steps of:

setting a data type bit within said register on being accessed by each of said processes and subsequently resetting said data type bit within said register;

restoring each of said set data type bit and identifying its corresponding data type;

storing the output data of each of said processes within a memory cache; and

resetting said memory cache when the data type bit set by the last of said processes is reset.

14. A computer system programmed to cache data according to claim 13 , wherein said plurality of processes comprises application modules, which are initialised.

15. A computer system programmed to cache data according to claim 14 , wherein each of said application modules defines a functionality of an application.

16. A computer system programmed to cache data according to claim 14 , wherein said data type register, including at least said one data type and corresponding data type bit is generated by said initialisation of said processes.

17. A computer system programmed to cache data according to claim 14 , wherein said application module initialisation takes place at the start of said application.

18. A computer system programmed to cache data according to claim 14 , wherein said application module initialisation takes after said start of said application.

19. A computer readable medium having computer readable instructions executable by a computer, such that said computer performs the steps of:

setting a data type bit within a data type register, which includes at least one data type and a corresponding data type bit, on being accessed by each of a plurality of processes and subsequently resetting said data type bit within said register;

restoring each of said set data type bit and identifying its corresponding data type;

storing the output data of each of said processes within a memory cache; and

resetting said memory cache when the data type bit set by the last of said processes is reset.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2009
From: AUTODESK CANADA CO.
To: AUTODESK, INC.
Reel/Frame 022445/0222 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2005
From: AUTODESK CANADA INC.
To: AUTODESK CANADA CO.
Reel/Frame 016641/0922 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2002
From: DANAN, ITAI
To: AUTODESK CANADA INC.
Reel/Frame 013252/0677 →