IP Library › Granted Patent US 7,243,323
Granted Patent B2
US 7,243,323 · App. 10/231,384 · Granted Jul 10, 2007

Integrated circuit chip design

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Quick Facts
Patent No.
US 7,243,323
App. No.
10/231,384
Granted
Jul 10, 2007
Kind
B2
Abstract

Method of developing a model of a circuit design including the steps of generating four different path-tracing runs, creating four arcs from the four different path-tracing runs, and combining the four arcs into two separate models. Also, a method of adjusting timing of a clock signal provided to a first block and a second block where data signals travel via a first path from the first block to the second block and data signals travel via a second path from the second block to the first block and the time for the data signals to travel the first path is greater than the time for the data signals to travel the second path. The clock signal provided to the second block relative to the clock signal provided to the first block is delayed by an amount that is a function of the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.

Claims (4)

1. A method of adjusting timing of a clock signal provided to a first block and a second block where data signals travel via a first path from the first block to the second block and data signals travel via a second path from the second block to the first block and the time for the data signals to travel the first path is greater than the time for the data signals to travel the second path comprising the step of delaying the clock signal provided to the second block relative to the clock signal provided to the first block by an amount that is a function of the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.

2. The method of claim 1 wherein the clock signal is delayed by an amount that is a function of one half the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.

3. The method of claim 1 wherein the clock signal is delayed by an amount that is a function of the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.

4. The method of claim 1 wherein the clock signal is delayed by an amount that is one half the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2003
From: M DISSOLUTION CORPORATION (FORMERLY KNOWN AS MORPHICS TECHNOLOGY, INC.)
To: INFINEON TECHNOLOGIES AG
Reel/Frame 014146/0100 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2002
From: WILLIAMS, TED E.; FERRO, JONATHAN; TOVEY, DEFOREST; TSENG, LOUIS
To: MORPHICS TECHNOLOGY, INC.
Reel/Frame 013480/0423 →