IP Library Granted Patent US 6,949,330
Granted Patent B2
US 6,949,330 · App. 10/231,918 · Granted Sep 27, 2005

Multiple level photolithography

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,949,330
App. No.
10/231,918
Granted
Sep 27, 2005
Kind
B2
Abstract

A method is provided for performing photolithography on a substrate which has a first region on a lower level and a second region on an upper level, wherein a first pattern area exists within said first region, a second pattern area exists within said second region, and at least said first and second regions are coated with a photoresist, the method comprising: a) exposing the photoresist through a first mask so as to expose said first region including said first pattern area, and thus create a first pattern in said first pattern area, but not expose said second pattern area; and b) exposing the photoresist through a second mask so as to expose said second pattern area, and thus create a second pattern in said second pattern area, but not expose said first pattern area, and also to expose an area of said first region which lies adjacent said second region.

Claims (11)

1. A method of performing photolithography on a substrate which has a first region on a lower level and a second region on an upper level, wherein a first pattern area exists within said first region, a second pattern area exists within said second region, and at least said first and second regions are coated with a photoresist, the method comprising:

a) exposing the photoresist through a first mask so as to expose said first region including said first pattern area, and thus create a first pattern in said first pattern area, but not expose said second pattern area; and

b) exposing the photoresist through a second mask so as to expose said second pattern area, and thus create a second pattern in said second pattern area, but not expose said first pattern area, and also to expose an area of said first region which lies adjacent said second region.

2. The method as claimed in claim 1 , wherein step (b) is carried out before step (a).

3. The method as claimed in claim 1 , wherein said first region is a recessed region which lies within said second region.

4. The method as claimed in claim 3 , wherein said area of said first region which is exposed in step (b) is a boundary area which lies around the edges of said first region.

5. The method as claimed in claim 4 , wherein said first and second patterns are substantially identical.

6. The method as claimed in claim 4 , wherein said boundary area extends along the entire edge of said first region, and exposing said boundary region in step (b) comprising exposing the entire boundary region.

7. The method as claimed in claim 1 , wherein said upper and lower levels are separated by approximately 2 microns.

8. The method as claimed in claim 1 , wherein in step (a) said first mask covers the whole of said second region.

9. The method as claimed claim 8 , wherein said first and second masks are the same mask, provided with patches in different positions.

Assignments (3)
CHANGE OF NAME Recorded Apr 22, 2019
From: X-FAB SEMICONDUCTOR FOUNDRIES AG
To: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
Reel/Frame 048956/0454 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2008
From: ZARLINK SEMICONDUCTOR LIMITED
To: X-FAB SEMICONDUCTOR FOUNDRIES AG
Reel/Frame 021511/0137 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2002
From: MARTIN, BRIAN; PERRING, JOHN; SHANNON, JOHN
To: ZARLINK SEMICONDUCTOR LIMITED
Reel/Frame 013433/0408 →