SIMD processor with a subroutine control unit
View Patent ↗The invention relates to a method and an apparatus for controlling a digital signal processor having a number of arithmetic units ( 1 a, 1 b ) which process a program ( 8 ). A control unit ( 5 ) is provided for independent control of the individual arithmetic units ( 1 a, 1 b ), which control unit ( 5 ) reads and evaluates the flags ( 9 a , 9 b ) which are specific to the arithmetic units, and deactivates those arithmetic units ( 1 a, 1 b ) whose associated flag is not set, so that a subroutine is carried out only by those arithmetic units ( 1 a, 1 b ) whose flags are set.
1. A method for controlling a digital signal single instruction multiple data (SIMD) processor, having a number of arithmetic units the method comprising:
(a) processing one program simultaneously on each of a number of arithmetic units so that a number of data streams are processed in parallel,
(b) reading and evaluating flags which are specific to specific arithmetic units,
(c) switching off the arithmetic units whose associated flag is not set and calling a subroutine by the program, which is carried out by the arithmetic units whose flag is set, if at least one of the flags is set,
(d) switching on the arithmetic units which have been switched off once the subroutine has been processed, and
(e) refraining from calling the subroutine and refraining from switching off the arithmetic units if none of the flags are set.
2. The method as claimed in claim 1 , wherein the arithmetic units are switched off by switching off a system clock for the arithmetic units.
3. The method as claimed in claim 1 , wherein a control unit produces a switching-off signal when a flag is not set.
4. The method as claimed in claim 1 , wherein the flag of an arithmetic unit is set when a predetermined condition occurs.
5. A digital signal single instruction multiple data (SIMD) signal processor having a number of arithmetic units and having a memory for one program which is processed simultaneously by each one of the arithmetic units so that a number of data streams are processed in parallel, distinguished by a control unit which is connected to the arithmetic units to switch off one or more of the arithmetic units if at least one of a plurality of flags is set which are specific to specific arithmetic units, wherein the digital signal processor is configured such that the one or more of the arithmetic units which are switched off do not implement a subroutine called by the program, wherein the digital signal processor is further configured to refrain from calling the subroutine and refraining from switching off the arithmetic units if none of the flags are set, and wherein the control unit is configured to switch on the arithmetic units which have been switched off once the subroutine has been processed.
6. The digital signal processor as claimed in claim 5 , wherein an arithmetic unit is switched off when an associated flag, which is specific to that arithmetic unit, is not set.
7. The method as claimed in claim 1 , wherein switching on the arithmetic units comprises switching on the arithmetic units which have been switched off in response to a return command that is carried out once the subroutine has been processed.
8. The digital signal processor as claimed in claim 5 , wherein the control unit is configured to switch on the arithmetic units which have been switched off in response to a return command that is carried out once the subroutine has been processed.