Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
View Patent ↗After formation of Cu interconnections 46 a to 46 e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46 a to 46 e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
1. A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first interconnection groove in a first interlayer insulating film over a first main surface of a wafer;
(b) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection groove;
(c) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove;
(d) removing the first interconnection metal film outside the first interconnection groove by first chemical mechanical polishing using slurry containing abrasive grains in an amount of less, than 0.5 wt. %;
(e) removing the first barrier metal film outside the first interconnection groove by second chemical mechanical polishing; and thereafter
(f) performing ammonia plasma treatment to the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film; and thereafter
(g) forming a copper diffusion barrier insulating film over the first main surface.
2. The method according to claim 1 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount smaller by one order of magnitude than that of the second chemical mechanical polishing.
3. The method according to claim 2 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount smaller by two orders of magnitude than that of the second chemical mechanical polishing.
4. The method according to claim 3 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount of less than 0.1 wt. %.
5. The method according to claim 4 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount of less than 0.01 wt. %.
6. The method according to claim 1 , wherein the second chemical mechanical polishing is performed using slurry containing abrasive grains in an amount of not less than 0.5 wt. %.
7. A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first interconnection groove in a first interlayer insulating film over a first main surface of a wafer;
(b) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection groove;
(c) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove;
(d) removing the first interconnection metal film outside the first interconnection groove by selective first chemical mechanical polishing using the first barrier metal film as a stop layer;
(e) removing the first barrier metal film outside the first interconnection groove by second chemical mechanical polishing; and thereafter
(f) performing ammonia plasma treatment of the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film; and thereafter
(g) forming a copper diffusion barrier insulating film over the first main surface.
8. A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first interconnection region in a first interlayer insulating film over a first main surface of a wafer;
(b) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection region;
(c) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection region so as to fill the first interconnection region;
(d) removing the first interconnection metal film outside the first interconnection region by first chemical mechanical polishing using slurry containing abrasive grains in an amount of less than 0.5 wt. %;
(e) removing the first barrier metal film outside the first interconnection region by second chemical mechanical polishing; and thereafter
(f) performing ammonia plasma treatment to the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film; and thereafter
(g) forming a copper diffusion barrier insulating film over the first main surface.
9. The method according to claim 8 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount smaller by one order of magnitude than that of the second chemical mechanical polishing.
10. The method according to claim 9 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount smaller by two orders of magnitude than that of the second chemical mechanical polishing.
11. The method according to claim 10 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount of less than 0.1 wt. %.
12. The method according to claim 11 , wherein the first chemical mechanical polishing is performed using slurry containing abrasive grains in an amount of less than 0.01 wt. %.
13. The method according to claim 8 , wherein the second chemical mechanical polishing is performed using slurry containing abrasive grains in an amount of not less than 0.5 wt. %.
14. A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first interconnection region in a first interlayer insulating film over a first main surface of a wafer;
(b) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection region;
(c) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection region so as to fill the first interconnection region;
(d) removing the first interconnection metal film outside the first interconnection region by selective first chemical mechanical polishing using the first barrier metal film as a stop layer;
(e) removing the first barrier metal film outside the first interconnection region by second chemical mechanical polishing; and thereafter
(f) performing ammonia plasma treatment of the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film; and thereafter
(g) forming a copper diffusion barrier insulating film over the first main surface.