Display apparatus
View Patent ↗A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13 , a drain electrode 10 connected to a pixel electrode 9 , a semiconductor layer 4 formed below the source electrode 6 , the source line 13 , and the drain electrode 10 , a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13 , and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.
1. A display apparatus comprising;
a gate line driving a pixel electrode constituting pixels on an insulating substrate;
a source line intersecting with said gate line with an insulating film in between;
a source electrode connected to said source line;
a drain electrode located opposite to said source electrode above a gate electrode connected to said gate line, and connected to said pixel electrode;
a semiconductor layer formed below said source electrode, said source line, and said drain electrode;
a light-shielding pattern configured below said semiconductor layer lying below said source line; and
a backlight emitting lights from a light source to strike a surface of said insulating substrate opposite to where pixels are formed.
2. A display apparatus according to claim 1 , wherein said light-shielding pattern is configured in a region outside of a crossing point of said gate line and said source line.
3. A display apparatus comprising:
a gate line driving a pixel electrode constituting pixels on an insulating substrate;
a source line intersecting with said gate line with an insulating film in between;
a source electrode connected to said source line;
a drain electrode located opposite to said source electrode above a gate electrode connected to said gate line, and connected to said pixel electrode;
a semiconductor layer formed below said source electrode, said source line, and said drain electrode;
a light-shielding pattern configured below said semiconductor layer lying below said source line; and
a backlight emitting lights from a light source to strike a surface of said insulating substrate opposite to where pixels are formed,
wherein said drain electrode further has an extending pattern which is configured not above said gate electrode nor above said gate line and which is connected to said pixel electrode, and said light-shielding pattern is configured not below said source line but below said semiconductor layer lying below a part or all of a region of said extending pattern of said drain electrode.
4. A display apparatus according to claim 1 , wherein said drain electrode further has an extending pattern which is configured not above said gate electrode nor above said gate line and which is connected to said pixel electrode, and said light-shielding pattern is configured below said semiconductor layer lying below said source line and said extending pattern of said drain electrode.
5. A display apparatus according to claim 2 , 3 , or 4 , wherein said light-shielding pattern is configured in the same layer of a conductive film as said gate line.
6. A display apparatus according to claim 3 or 4 , wherein a connecting pattern, which connects a connection between said extending pattern of said drain electrode and said pixel electrode with said drain electrode, is configured narrower than a channel width of a thin film transistor which are configured from said gate electrode, an insulating film, said source electrode, said drain electrode, and said semiconductor layer.
7. A display apparatus according to claim 1 , wherein said shielding pattern is disposed apart from a crossing point of said gate line and said source line.
8. A display apparatus according to claim 1 , wherein said shielding pattern is formed in substantially all regions in which said semiconductor layer lies below said source line and is outside of said gate electrode and said gate line.