Unified memory address generation system and method for fetching and storing MPEG video data
View Patent ↗A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.
1. A method for decoding a plurality of video frames, the method comprising the steps of:
using an n-bit counter to generate up to 2 n number of distinct bit pattern sequences, wherein n is a positive integer and wherein each of the 2 n distinct bit pattern sequences is associated with a distinct binary value comprising n bits;
generating up to n factorial number of non-sequential bit pattern sequences from the 2 n number of distinct bit pattern sequences by swapping a pair of bits in each of the 2 n distinct binary values comprising n bits;
selecting one or more of the n factorial number of non-sequential bit pattern sequences to create one or more corresponding addressing schemes; and
fetching and storing data that is associated with the plurality of video frames using the one or more addressing schemes.
2. The method of claim 1 , wherein:
the step of using an n-bit counter to generate up to 2 n number of distinct bit pattern sequences further comprises the step of using the n-bit counter to produce a first sequence of 2 n number of sequential numbers, wherein each of the 2 n sequential numbers is associated with a one of the distinct binary values comprising n bits;
the pair of bits in each of the 2 n distinct binary values comprised in the step of generating comprises an mth pair of bits, wherein m is an integer that ranges in value from 1 to (n!−1); and
the step of swapping the pair of bits in each of the 2 n distinct binary values comprised in the step of generating further comprises swapping the mth pair of bits in each binary value to produce an (m1 )th sequence of 2 n number of non-sequential numbers.
3. The method of claim 1 , wherein the step of selecting one or more of the n factorial number of non-sequential bit pattern sequences further comprises the step of using one or more corresponding multiplexers for selecting the one or more of the n factorial number of non-sequential bit pattern sequences.
4. The method of claim 1 , wherein the step of selecting one or more of the n factorial number of non-sequential bit pattern sequences further comprises the step of applying a combinational logic to one or more bits of the n-bit counter.
5. The method of claim 1 , wherein the one or more addressing schemes is based on one or more corresponding flags and conditions that are associated with the plurality of video frames.
6. A computer-readable medium carrying one or more sequences of instructions for decoding data from a plurality of video frames in a computer system, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:
using an n-bit counter to generate up to 2 n number of distinct bit pattern sequences, wherein n is a positive integer and wherein each of the 2 n distinct bit pattern sequences is associated with a distinct binary value comprising n bits;
generating up to n factorial number of non-sequential bit pattern sequences from the 2 n number of distinct bit pattern sequences by swapping a pair of bits in each of the 2 n distinct binary values comprising n bits;
selecting one or more of the n factorial number of non-sequential bit pattern sequences to create one or more corresponding addressing schemes; and
fetching and storing data that is associated with the data from the plurality of video frames using the one or more addressing schemes.
7. An apparatus for decoding a plurality of video frames, comprising:
one n-bit counters, wherein the n-bit counter generates up to 2 n number of distinct bit pattern sequences, wherein n is a positive integer;
other address generator circuitry for generating up to n factorial number of non-sequential bit pattern sequences from the 2 n number of distinct bit pattern sequences by swapping a pair of bits in each of 2 n respectively associated distinct binary values comprising n bits; and
one or more multiplexers corresponding to the n-bit counters for selecting one or more of the n factorial number of non-sequential bit pattern sequences to create one or more corresponding addressing schemes associated with the plurality of video frames.
8. The apparatus of claim 7 , further comprising one or more motion compensation units that are associated with the n-bit counters and the one or more corresponding multiplexers.
9. The apparatus of claim 7 , further comprising one or more merge-and-store units that are associated with the n-bit counters and the one or more corresponding multiplexers.
10. The apparatus of claim 7 , further comprising one or more intracoded direct cosine units that are associated with the n-bit counters and the one or more corresponding multiplexers.
11. The apparatus of claim 7 , wherein:
the one or more corresponding addressing schemes are used for fetching and storing data that is associated with the plurality of video frames.
12. The method of claim 7 , wherein the one or more addressing schemes is based on corresponding one or more flags and conditions that are associated with the plurality of video frames.