Integrated circuit die having an interference shield
View Patent ↗A package for housing a device (e.g., an integrated circuit chip or die) includes a Faraday cage. The Faraday cage is at least partially formed in the integrated circuit die. The die includes conductive vias and solder balls surrounding a circuit. The package can be a ball grid array (BGA) package or flip chip package. The package substrate can include a ground plane.
1. A process of manufacturing an integrated circuit package, comprising:
providing an integrated circuit including a first circuit, and at least one second circuit, the first circuit being surrounded on lateral sides by a plurality of conductive vias; and
providing a package substrate having a ground plane, whereby the conductive vias and ground plane protect the second circuit from electromagnetic interference from the first circuit, wherein the integrated circuit includes a plurality of metal layers and wherein the vias extend through all of the metal layers, wherein the integrated circuit further includes a semiconductor substrate above the metal layers, wherein the semiconductor substrate is on a top end and the metal layers are on a bottom end, the bottom end being adjacent the package substrate.
2. The process of claim 1 , the conductive electrically coupling the conductive vias to the ground plane.
3. The process of claim 2 , wherein the conductive vias are coupled to the ground plane by solder balls.
4. The process of claim 1 , wherein the package substrate is a ball grid array substrate.
5. The process of claim 1 , further comprising:
providing a conductive cover above the integrated circuit.
6. The process of claim 1 , wherein the first circuit is an oscillator.
7. A process of manufacturing an integrated circuit package, comprising:
providing an integrated circuit including a first circuit, and at least one second circuit, the first circuit being surrounded on lateral sides by a plurality of conductive vias; and
providing a package substrate having a ground plane, whereby the conductive vias and ground plane protect the second circuit from electromagnetic interference from the first circuit, wherein the integrated circuit includes a plurality of metal layers and wherein the vias extend through all of the metal layers, wherein the first circuit includes an inductor disposed in one of the metal layers, the one metal layer being a metal layer farthest from the semiconductor substrate.
8. The process of claim 7 , wherein the integrated circuit includes a plurality of metal layers and wherein the vias extend through all of the metal layers.
9. The process of claim 7 , wherein the integrated circuit further includes a semiconductor substrate above the metal layers, wherein the semiconductor substrate is on a top end and the metal layers are on a bottom end, the bottom end being adjacent the package substrate.
10. A method of manufacturing a packaged integrated circuit including a first circuit and a second circuit, the method comprising:
providing a semiconductor substrate;
providing a plurality of metal layers; and
providing a plurality of conductive vias, wherein the first circuit is within a perimeter defined by the conductive vias and a second circuit is disposed outside of the perimeter, whereby the conductive vias provide electromagnetic shielding; and
electrically coupling the conductive vias to a package substrate, wherein the package substrate is a ball grid array package substrate having a ground plane extending at least over an area within the perimeter and the conductive vias are coupled to the ground plane.
11. The method of claim 10 , wherein the first circuit includes an oscillator operating in a GHZ range.
12. The method of claim 10 , wherein the metal layers include an inductor, the inductor being part of the first circuit.
13. The method of claim 12 , wherein the semiconductor substrate includes a transistor.
14. The method of claim 13 , wherein the first circuit includes an oscillator.
15. The method of claim 14 , wherein the oscillator operates in a frequency range in the GHZ range.
16. The method of claim 10 , wherein the circuit includes an oscillator.
17. A method of providing a Faraday cage for an integrated circuit die contained in a package, the method comprising:
providing conductive vias about a periphery of a first circuit in the integrated circuit dies wherein a second circuit is outside the periphery and protected from interference from the first circuit; and
mounting the integrated circuit die on a package substrate, the conductive vias being electrically coupled to a conductive plane of the package substrate, wherein the integrated circuit die includes metal layers, the vias being disposed through the metal layers, wherein the integrated circuit further includes a semiconductor substrate above the metal layers, wherein the semiconductor substrate is on a top end and the metal layers are on a bottom end, the bottom end being adjacent the package substrate.
18. The method of claim 17 , wherein the conductive plane is a ground plane.
19. The method of claim 17 , wherein the first circuit includes an inductor in the metal layers.
20. The method of claim 19 , wherein the circuit is coupled to at least one other circuit on the circuit die, the at least one other circuit being located outside the periphery.