Granted Patent B2

US 6,957,376 · App. 10/244,642 · Granted Oct 18, 2005

Abstract

Claims (33)

1. A turbo decoder assembly for decoding a data signal error-protection-coded with a turbo code based on parallel concatenated convolutional codes with interleaving at a transmitter end, transmitted via a disturbed transmission channel, and received in a receiver, comprising:

a turbo decoder having a first computing device, a second computing device, and a bidirectional interface connected between said first and second computing devices for transferring data between said first and second computing devices, said turbo decoder being configured to iteratively decode a data signal received in the receiver in a computing loop, to be passed a plurality of times, and performing the following computing steps:

(a) first symbol estimation of an input data signal, taking into consideration a first partly redundant data signal and a feedback data signal;

(b) interleaving of the data signal calculated in the first symbol estimation;

(c) second symbol estimation of the interleaved data signal, taking into consideration a second partly redundant data signal; and

(d) deinterleaving the data signal calculated in the second symbol estimation, for determining the feedback data signal;

said first computing device being configured to carry out steps (a) and (c), said first computing device including only one hardware-based symbol estimator being alternately used for carrying out computing steps (a) and (c); and

said second computing device being configured to carry out steps (b) and (d), said second computing device being a software-based digital signal processor.

2. The turbo decoder according to claim 1 , wherein:

said computing loop contains a further computing step of calculating statistical information representing an instantaneous channel state; and

said second computing device is configured to carry out the further computing step.

3. The turbo decoder according to claim 1 , wherein said bidirectional interface has two DMA channels allocated thereto.

4. The turbo decoder according to claim 1 , wherein:

said first computing device is configured to calculate, with knowledge of the error protection code used at the transmitter end:

transition metric values;

forward and reverse recursion metric values; and therefrom,

output values that are representative of a probability with which a data symbol of the detected data signal to be estimated has a particular value; and

said first computing device contains a hardware computing chip, constructed of combinatorial logic, for generating at least one type of the values.

5. The turbo decoder according to claim 4 , wherein said first computing device comprises:

a first hardware computing chip, constructed of combinatorial logic, for generating the transition metric values;

a second hardware computing chip, constructed of combinatorial logic, for generating the forward and reverse recursion metric values; and

a third hardware computing chip, constructed of combinatorial logic, for generating the output values.

6. A method for turbo decoding a data signal error-protection-coded with a turbo code based on parallel concatenated convolutional codes with interleaving at a transmitter end, transmitted via a disturbed channel, and detected in a receiver, the method which comprises:

iteratively decoding the data signal detected in the receiver in a computing loop, to be passed several times and containing the following computing steps:

(a) first symbol estimation of an input data signal, taking into consideration a first partly redundant data signal and a feedback data signal,

(b) interleaving of the data signal calculated in the first symbol estimation,

(c) second symbol estimation of the interleaved data signal, taking into consideration a second partly redundant data signal, and

(d) deinterleaving the data signal calculated in the second symbol estimation, for determining the feedback data signal;

and thereby computing steps (a) and (c) in a first computing device by carrying out the computing steps (a) and (c) with only one hardware-based symbol estimator in the first computing device being alternately used for carrying out computing steps (a) and (c), and computing steps (b) and (d) in a second computing device by carrying out the computing steps (b) and (d) by processing a program with a digital signal processor; and

performing within one computing loop pass, two bidirectional data transfer operations between the first and second computing devices.

7. The method according to claim 6 , which comprises carrying out the computing steps by a first computing device that is substantially constructed in hardware.

8. The method according to claim 6 , which comprises carrying out the computing steps by a first computing device that is completely constructed in hardware.

9. The method according to claim 6 , which comprises effecting the data transfer by a direct memory access.

Assignments (6)