Semiconductor device including memory cells and manufacturing method thereof

1. A method for fabricating a semiconductor device, comprising:

preparing a semiconductor substrate;

forming a first memory cell on the semiconductor substrate, wherein the first memory cell includes a first capacitor and a first MOS transistor having a gate electrode, a source region and a drain region;

forming a second memory cell on the semiconductor substrate, wherein the second memory cell includes a second capacitor and a second MOS transistor, wherein the second MOS transistor is formed in a vicinity of the first MOS transistor and has a gate electrode, a source region and a drain region, and wherein one of the source and drain regions of the first MOS transistor and one of the source and drain regions of the second MOS transistor is a shared region;

forming a peripheral circuit on the semiconductor substrate, wherein the peripheral circuit includes a third MOS transistor having a gate electrode, a source region and a drain region;

forming a nitride layer so as to cover the first, second and third MOS transistors;

forming a side wall on the gate electrode of the third MOS transistor by etching the nitride layer on the third MOS transistor;

depositing a refractory metal layer on the semiconductor substrate; and

exposing the refractory metal layer to a heat treatment so as to form a refractory metallic silicide from the refractory metal and silicon on the source region and the drain region of the third MOS transistor,

wherein the gate electrodes of the first, second and third MOS transistors are formed of a polycrystalline silicon, a second refractory metal and a compound made up of the second refractory metal and nitrogen, and wherein a compound layer containing the compound is sandwiched between a polycrystalline silicon layer containing the polycrystalline silicon and a second refractory metallic layer containing the second refractory metal.

2. The method according to claim 1 , further comprising:

removing the nitride layer on the first and second MOS transistors; and

forming an oxide layer so as to cover the first and second MOS transistors.

3. The method according to claim 1 , further comprising:

connecting a bit line to the shared region;

connecting another one of the source and drain regions of the first MOS transistor to the first capacitor; and

connecting another one of the source and drain regions of the second MOS transistor to the second capacitor,

wherein data is readable out from the first and second memory cells via the bit line.

4. A method for fabricating a semiconductor device, comprising:

preparing a semiconductor base having a principal surface;

forming a memory cell on the principal surface, the memory cell including a capacitor and a first MOS transistor, wherein the first MOS transistor has a source region, a drain region and a gate electrode; and

forming a peripheral circuit on the principal surface, the peripheral circuit controlling the memory cell and including a second MOS transistor that has a source region, a drain region and a gate electrode,

said forming a memory cell and said forming a peripheral circuit comprises

forming the gate electrodes of the first and second MOS transistors of a polycrystalline silicon, a first refractory metal, and a compound layer of the first refractory metal and nitrogen, wherein the compound layer is sandwiched between the polycrystalline silicon and the first refractory metal,

forming the source and drain regions of the second MOS transistor of a silicide of a second refractory metal, and

forming the source and drain regions of the first MOS transistor so as not to include the first and second refractory metals.

5. The method according to claim 4 , wherein the first and second refractory metals are a same metal.

6. The method according to claim 4 , wherein said forming a peripheral circuit comprises forming the source and drain regions of the second MOS transistor as each having a lightly doped drain (LDD) structure.

7. A method of manufacturing a semiconductor device comprising:

preparing a semiconductor substrate having a memory cell region and a peripheral region;

forming a gate insulating layer on the semiconductor substrate in the memory cell region and the peripheral region;

forming a plurality of gate electrodes and a plurality of insulating patterns on the gate insulating layer;

forming a plurality of source/drain regions on the semiconductor substrate in the memory cell region and the peripheral region;

forming a plurality of side wall structures on the gate electrodes and the insulating patterns, wherein the source/drain regions in the memory cell region are covered by the side wall structures and the source/drain regions in the peripheral region are exposed;

forming a plurality of first silicide regions on the exposed source/drain regions in the peripheral region;

removing the insulating patterns so as to expose the gate electrodes; and

forming a plurality of second silicide regions on the exposed gate electrodes.

8. A method of manufacturing a semiconductor device according to claim 7 , further comprising:

forming an interlayer insulating layer on the second suicide regions; and

forming a plurality of capacitor structures on the interlayer insulating layer.

9. A method of manufacturing a semiconductor device according to claim 7 , wherein said forming a plurality of first silicide regions includes:

forming a refractory metal layer on the exposed source/drain regions in the peripheral region of the semiconductor substrate; and

reacting the refractory metal layer with the source/drain regions so as to form the first silicide regions.

10. A method of manufacturing a semiconductor device according to claim 7 , wherein said forming a plurality of source/drain regions and said forming a plurality of side wall structures include:

forming a plurality of lightly doped source/drain regions in the semiconductor substrate in the memory cell region and the peripheral region;

forming the side wall structures on the gate electrodes and the insulating patterns, wherein the lightly doped source/drain regions in the memory cell region are covered by the side wall structures and the lightly doped source/drain regions in the peripheral region are exposed; and

forming a plurality of heavily doped source/drain regions in the lightly doped source/drain regions in the peripheral region using the side wall structures as a mask.

11. A method of manufacturing a semiconductor device according to claim 10 , wherein the first silicide regions are formed on the heavily doped source/drain regions.

12. A method of manufacturing a semiconductor device according to claim 7 , wherein the insulating patterns are silicon nitride patterns.

13. A method of manufacturing a semiconductor device according to claim 7 , wherein said forming a plurality of second suicide regions includes:

forming a refractory metal layer on the exposed gate electrodes; and

reacting the refractory metal layer with the gate electrodes so as to form the second silicide regions.