IP Library Granted Patent US 6,867,479
Granted Patent B2
US 6,867,479 · App. 10/247,575 · Granted Mar 15, 2005

Method for rewiring pads in a wafer-level package

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Quick Facts
Patent No.
US 6,867,479
App. No.
10/247,575
Granted
Mar 15, 2005
Kind
B2
Abstract

A method for rewiring contact pads in the wafer-level package is inventively provided. In order to be able to make the terminals of the characterization pads available for testing in a wafer-level package without these terminals being available later to the end user, the invention provides that the rewiring line is led via the scribe line of the wafer.

Claims (23)

1. A method for rewiring contact pads of a chip, which comprises:

placing the chip on a wafer in a wafer-level package, the wafer-level package having a wiring layer with terminal pins; and

leading a rewiring line via a scribe line of the wafer to electrically connect one of the contact pads to one of the terminal pins.

2. The method according to claim 1 , wherein:

a majority of a length of the rewiring line is led on the scribe line.

3. A semiconductor chip in combination with a wafer-level package, comprising:

contact pads;

terminal pins as part of the wafer-level package;

a scribe line; and

at least one rewiring line for electrically connecting one of said contact pads to one of said terminal pins during testing before said scribe line is sawed;

said rewiring line being led via said scribe line so that said rewiring line will be interrupted when said scribe line is sawed.

4. A semiconductor chip in combination with a wafer-level package, comprising:

contact pads;

terminal pins as part of the wafer-level package;

a sawn edge obtained by sawing a scribe line; and

at least one rewiring line configured for electrically connecting one of said contact pads to one of said terminal pins during testing before sawing said scribe line;

said rewiring line being led to said edge such that said rewiring line is interrupted after said scribe line was sawed.

5. A semiconductor chip in combination with a wafer-level package, comprising:

contact pads;

terminal pins as part of the wafer-level package;

a sawn edge obtained by sawing a scribe line;

a portion of a rewiring line electrically connected to one of said contact pads and leading to said edge; and

a portion of a rewiring line electrically connected to one of said terminal pins and leading to said edge.