Method of forming a low temperature polysilicon thin film transistor
View Patent ↗The present invention provides a method of forming a low temperature polysilicon thin film transistor (LTPS TFT). A polysilicon layer including a channel region is formed first. A first and a second plasma enhanced chemical vapor deposition processes are sequentially performed to form a composite gate insulating layer composed of a TEOS-based silicon oxide layer and a silicon nitride layer on the channel region. Finally a gate electrode and a source/drain of the low temperature polysilicon thin film transistor are formed.
1. A method of forming at least one low temperature polysilicon thin film transistor (LTPS TFT) on an insulating substrate, the method comprising:
forming at least one polysilicon layer (poly-Si layer) on a surface of the insulating substrate, a source region, a drain region, and a channel region of the low temperature polysilicon thin film transistor being comprised on a surface of the polysilicon layer;
performing a first plasma enhanced chemical vapor deposition (PECVD) process and a second plasma enhanced chemical vapor deposition process to sequentially form a tetra-ethyl-ortho-silicate based silicon oxide layer (TEOS-based SiO x layer, where x≈2) and a silicon nitride layer (SiN x layer, where 1.0<x<1.6) on the channel region, the tetra-ethyl-ortho-silicate based silicon oxide layer situated on the surface of the polysilicon layer and the silicon nitride layer form a composite gate insulating layer; and
forming a gate electrode on the composite gate insulating layer.
2. The method of claim 1 wherein the insulating substrate is a glass substrate.
3. The method of claim 1 wherein the insulating substrate is a quartz substrate.
4. The method of claim 1 wherein the method for forming the polysilicon layer further comprises the following steps:
performing a sputtering process to form an amorphous silicon layer (α-Si layer) on the surface of the insulating substrate; and
performing an annealing process to re-crystallize the amorphous silicon layer to the polysilicon layer.
5. The method of claim 4 wherein the annealing process is an excimer laser annealing (ELA) process.
6. The method of claim 1 wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in a single wafer type chamber continuously.
7. The method of claim 1 wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in different single wafer type chambers.
8. The method of claim 1 wherein the tetra-ethyl-ortho-silicate based silicon oxide layer in the composite gate insulating layer is used to improve the interface property between the polysilicon layer and the composite gate insulating layer.
9. The method of claim 1 wherein the silicon nitride layer in the composite gate insulating layer is used to enhance the barrier ability of the composite gate insulating layer to moisture and metal ions.
10. The method of claim 1 wherein the thickness of the tetra-ethyl-ortho-silicate based silicon oxide layer is much greater than the thickness of the silicon nitride layer.
11. The method of claim 10 wherein the thickness of the tetra-ethyl-ortho-silicate based silicon oxide layer is much greater than the thickness of the silicon nitride layer to effectively reduce the parasitic capacitance.
12. The method of claim 10 wherein the thickness of the tetra-ethyl-ortho-silicate based silicon oxide layer is approximately 500˜1200 angstrom (Å), the thickness of the silicon nitride layer is approximately 100˜500 angstrom (Å).
13. The method of claim 1 wherein the material composition of the gate electrode is tungsten (W).
14. The method of claim 1 wherein the material composition of the gate electrode is chrome (Cr).
15. The method of claim 1 wherein an ion implantation process is performed by utilizing the gate electrode as a mask after forming the gate electrode to form a source electrode and a drain electrode in the polysilicon layer in the source region and in the drain region, respectively.
16. The method of claim 15 wherein an activation process is performed after the ion implantation process to activate the dopants in the source electrode and the drain electrode.
17. A method of forming a gate insulating layer of a low temperature polysilicon thin film transistor (LTPS TFT), the method comprising:
forming a patterned polysilicon layer (poly-Si layer);
performing a first plasma enhanced chemical vapor deposition (PECVD) process to directly form a first dielectric layer composed of tetra-ethyl-ortho-silicate based silicon oxide (TEOS-based SiO x , where x≈2) on a surface of the polysilicon layer;
performing a second plasma enhanced chemical vapor deposition process to directly form a second dielectric layer composed of silicon nitride (SiN y , where 1.0<y<1.6) on a surface of the first dielectric layer; and
forming a patterned gate electrode on a surface of the second dielectric layer directly;
wherein the gate insulating layer is composed of the first dielectric layer and the second dielectric layer.
18. The method of claim 17 wherein the method for forming the polysilicon layer further comprises the following steps:
performing a sputtering process to form an amorphous silicon layer (α-Si layer); and
performing an annealing process to re-crystallize the amorphous silicon layer to the polysilicon layer.
19. The method of claim 18 wherein the annealing process is an excimer laser annealing (ELA) process.
20. The method of claim 17 wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in a single wafer type chamber continuously.
21. The method of claim 17 wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in different single wafer type chambers.
22. The method of claim 17 wherein the thickness of the first dielectric layer is approximately 500˜1200 angstrom (Å) and the thickness of the second dielectric layer is approximately 100˜500 angstrom (Å).
23. The method of claim 17 wherein the material composition of the gate electrode is tungsten (W).
24. The method of claim 17 wherein the material composition of the gate electrode is chrome (Cr).
25. The method of claim 17 wherein the first dielectric layer in the gate insulating layer is used to improve the interface property between the polysilicon layer and the gate insulating layer, the second dielectric layer in the gate insulating layer is used to enhance the barrier ability of the gate insulating layer to moisture and metal ions.
26. A method of forming a gate insulating layer of a low temperature polysilicon thin film transistor (LTPS TFT), the method comprising:
forming a patterned gate electrode;
performing a first plasma enhanced chemical vapor deposition (PECVD) process to directly form a first dielectric layer composed of silicon nitride (SiN y , where 1.0<y<1.6) on a surface of the gate electrode;
performing a second plasma enhanced chemical vapor deposition process to directly form a second dielectric layer composed of tetra-ethyl-ortho-silicate based silicon oxide (TEOS-based SiO x , where x≈2) on a surface of the first dielectric layer; and
forming a patterned polysilicon layer (poly-Si layer) on a surface of the second dielectric layer directly;
wherein the gate insulating layer is composed of the first dielectric layer and the second dielectric layer.
27. The method of claim 26 wherein the material composition of the gate electrode is tungsten (W).
28. The method of claim 26 wherein the material composition of the gate electrode is chrome (Cr).
29. The method of claim 26 wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in a single wafer type chamber continuously.
30. The method of claim 26 wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in different single wafer type chambers.
31. The method of claim 26 wherein the thickness of the first dielectric layer is approximately 100˜500 angstrom (Å) and the thickness of the second dielectric layer is approximately 500˜1200 angstrom (Å).
32. The method of claim 26 wherein the method for forming the polysilicon layer further comprises the following steps:
performing a sputtering process to form an amorphous silicon layer (α-Si layer); and
performing an annealing process to re-crystallize the amorphous silicon layer to the polysilicon layer.
33. The method of claim 32 wherein the annealing process is an excimer laser annealing (ELA) process.
34. The method of claim 26 wherein the first dielectric layer in the gate insulating layer is used to enhance the barrier ability of the gate insulating layer to moisture and metal ions, the second dielectric layer in the gate insulating layer is used to improve the interface property between the polysilicon layer and the gate insulating layer.