Barrier material
View Patent ↗A barrier layer protecting, for example, a ferroelectric capacitor from hydrogen is described. The barrier layer comprises aluminum oxide with barrier enhancement dopants. The barrier enhancement dopants are selected from Ti, Hf, Zr, their oxides, or a combination thereof.
1. An integrated circuit (IC) comprising:
a circuit feature; and
a barrier layer covering at least part of the circuit feature, the barrier layer comprising aluminum oxide and barrier enhancing dopants, wherein the barrier enhancing dopants comprises Zr or Hr or a combination thereof.
2. The IC of claim 1 wherein the circuit feature comprises a capacitor.
3. The IC of claim 1 wherein the circuit feature comprises a ferroelectric capacitor.
4. The IC of claim 1 wherein the barrier enhancing dopants form a barrier enhancing dopant layer.
5. An IC comprising:
a circuit feature; and
a barrier layer covering at least part of the circuit feature, wherein a barrier layer comprises first and second aluminum oxide layers and a barrier enhancing dopant layer located between them.
6. The IC of claim 5 wherein the circuit feature comprises a capacitor.
7. The IC of claim 5 wherein the circuit feature comprises a ferroelectric capacitor.
8. The IC of claim 5 , 6 or 7 wherein the barrier enhancing dopant layer comprises Ti, Zr, or Hf, their oxides or a combination thereof.
9. An IC comprising:
a circuit;
a barrier layer covering at least part of the circuit feature, the barrier layer comprising aluminum oxide and barrier enhancing dopants;
a first dielectric layer is located below the circuit feature;
a second dielectric layer is located over the circuit feature; and
a lower barrier layer below the circuit feature, wherein the lower barrier layer is located in the first dielectric layer, the lower barrier layer comprises aluminum oxide and barrier enhancing dopants.
10. The IC of claim 9 wherein the barrier enhancing dopants of the lower barrier layer form a barrier enhancing dopant layer.
11. The IC of claim 10 wherein the lower barrier layer comprises first and second aluminum oxide layers and the barrier enhancing dopant layer located between them.
12. The IC of claim 9 wherein the barrier enhancing dopants are selected froth Ti, Zr, Hf, their oxides or a combination thereof.
13. The IC of claim 12 wherein the barrier enhancing dopants of the lower barrier layer form a barrier enhancing dopant layer.
14. The IC of claim 13 wherein the lower barrier layer comprises first and second aluminum oxide layers and the barrier enhancing dopant layer located between them.
15. The IC of claim 9 further comprises:
an upper barrier layer on the surface of the second dielectric layer.
16. The IC of claim 15 wherein the barrier enhancing dopants of the upper barrier layer form a barrier enhancing dopant layer.
17. The IC of claim 16 wherein the upper barrier layer comprises first and second aluminum oxide layers and the barrier enhancing dopant layer located between them.
18. The IC of claim 15 wherein the barrier enhancing dopants of the upper barrier layer are selected from Ti, Zr, Hf, their oxides or a combination thereof.
19. The IC of claim 18 wherein the barrier enhancing dopants of the upper barrier layer from a barrier enhancing dopant layer.
20. The IC of claim 19 wherein the upper barrier layer comprises first and second aluminum oxide layers and the barrier enhancing dopant layer located between them.
21. The IC of claim 4 wherein the barrier layer comprises first and second aluminum oxide layers and the barrier enhancing dopant layer beat between them.
22. The IC of claim 21 wherein the barrier enhancing dopant layer comprises barrier enhancing dopants or oxides thereof.
23. The IC of claim 22 wherein the barrier layer comprises first and second aluminum oxide layers and the barrier enhancing dopant layer located between them.
24. A method of forming an IC comprising:
providing a substrate having a circuit feature formed thereon;
forming a barrier layer on the substrate, the barrier layer covers at least a portion of the circuit feature, wherein forming the barrier layer comprises forming a barrier stack comprising first and second aluminum oxide layers separated by a barrier enhancing dopant layer.
25. A method of forming an IC comprising:
providing a substrate having a circuit feature formed thereon;
forming a barrier layer on the substrate, the barrier layer covers at least a portion of the circuit feature, wherein forming the barrier layer comprises forming an aluminum oxide layer doped with barrier enhancing dopants comprising Hf or Zr or a combination thereof.