Method of manufacturing a semiconductor integrated circuit device including a gate electrode having a salicide layer thereon

1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) depositing a first insulating film over a first conductive layer;

(b) patterning said first insulating film by using a resist film as a mask to form a cap film;

(c) removing said resist film;

(d) after said step (c), forming a gate electrode of a MISFET by etching said first conductive layer using said cap film as a mask;

(e) depositing a second insulating film over said gate electrode and said cap film;

(f) forming a side wall spacer on side surfaces of said gate electrode by etching said second insulating film; and

(g) after said step (f), selectively forming a salicide layer on said gate electrode,

wherein said cap film is removed in said step (f) by over-etching said first insulating film to etch said cap film.

2. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said first insulating film is comprised of a silicon oxide film, wherein said second insulating film is comprised of a silicon oxide film, and wherein said first conductive layer is comprised of a silicon film.

3. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising the steps of:

(h) before step (e), forming a first semiconductor region in a substrate; and

(i) after said step (f), forming a second semiconductor region in said substrate;

wherein in said step (g), sulicide layers are formed on both said second semiconductor region and said gate electrode,

wherein said first and second semiconductor region serves as a source or drain of said MISFET,

and wherein said second semiconductor region has an impurity concentration higher than said first semiconductor region.

4. A method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein said salicide film is cobalt silicide film.

5. A method of manufacturing a semiconductor integrated circuit device according to claim 4 , further comprising the steps of:

(i) before said step (c), forming a first semiconductor region in a substrate; and

(j) after said step (d), forming a second semiconductor region in said substrate;

wherein in said step (e), sulicide layers are formed on both said second semiconductor region and said gate electrode,

wherein said first and second semiconductor region serves as a source or drain of said MISFET, and

wherein said second semiconductor region has an impurity concentration higher than said first semiconductor region.

6. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) depositing a first insulating film over a silicon film;

(b) patterning said first insulating film by using a resist film as a mask to form a cap film;

(c) after said step (b), removing said resist film;

(d) forming a gate electrode of a MISFET by etching said first silicon film using said cap film as a mask;

(e) depositing a second insulating film over said gate electrode and said cap film,

wherein said second insulating film is comprised of the same material as said first insulating film;

(f) forming a side wall spacer on side surfaces of said gate electrode by etching said second insulating film; and

(g) after said step (f), selectively forming a cobalt salicide layer on said gate electrode, and

wherein said first cap film is removed in said step (f) by over-etching said first insulating film to etch said first cap film.

7. A method of manufacturing a semiconductor integrated circuit device according to claim 6 , wherein said first

insulating film is comprised of a silicon oxide film, and wherein said second insulating film is comprised of a silicon oxide film.

8. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising the steps of:

(h) before said step (g), depositing a third insulating film over said side wall spacer and a main surface of a substrate; and

(i) before said step (g), selectively removing said third insulating film such that at least a part of said third insulating film remains over a semiconductor region formed in said substrate.

9. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising the steps of:

(h) before said step (g), depositing a third insulating film over said side wall spacer and a conductive film formed with the same level layer as said first conductive layer; and

(i) before said step (g), selectively removing said third insulating film such that at least a part of said third insulating film remains over said conductive film.

10. A method of manufacturing a semiconductor integrated circuit device according to claim 9 , wherein said third insulating film remains to cover said conductive film.

11. A method of manufacturing a semiconductor integrated circuit device according to claim 10 , wherein said conductive film serves as a gate electrode of a further MISFET.

12. A method of manufacturing a semiconductor integrated circuit device according to claim 9 , wherein said conductive film serves as a gate electrode of a further MISFET.

13. A method of manufacturing a semiconductor integrated circuit device according to claim 10 , wherein said semiconductor region is electrically connected to a source or drain region of a further MISFET.

14. A method of manufacturing a semiconductor integrated circuit device according to claim 9 , wherein said semiconductor region is electrically connected to a source or drain region of a further MISFET.

15. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) depositing a first insulating film over a first conductive layer formed over a main surface of a substrate;

(b) patterning said first insulating by using a mask film to form a cap film;

(c) removing said mask film;

(d) after said step (c), forming a gate electrode of a MISFET by etching said first conductive layer using said cap film as a mask;

(e) depositing a second insulating film over said gate electrode and said cap film;

(f) forming a side wall spacer on side surfaces of said gate electrode by etching said second insulating film;

(g) depositing a third insulating film over said side wall spacer and said main surface;

(h) selectively removing said third insulating film such that said third insulating film remains over at least a part of a semiconductor region formed in said substrate; and

(i) after said step (h), selectively forming a salicide layer on said gate electrode such that a salicide layer is not formed over said part of said semiconductor region;

wherein said cap film is removed in said step (f) by over-etching said second insulating film to etch said cap film.

16. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) depositing a first insulating film over a first conductive layer formed over a main surface of a substrate;

(b) patterning said first insulating by using a mask film to form film;

(c) removing said mask film;

(d) after said step (c), forming a gate electrode of a MISFET by etching said first conductive layer using said cap film as a mask;

(e) depositing a second insulating film over said gate electrode and said cap film;

wherein said second insulating film includes the same material as said first insulating film;

(f) forming a side wall spacer on side surfaces of said gate electrode by etching said second insulating film;

(g) depositing a third insulating film over said side wall spacer and a conductive film formed over said main surface; and

(h) selectively removing said third insulating film such that at least a part of said third insulating film remains over said conductive film; and

(i) after said step (h), selectively forming a salicide layer on said gate electrode;

wherein said cap film is removed in said step (f) by over-etching said second insulating film to etch said cap film.

17. A method of manufacturing a semiconductor integrated circuit device according to claim 16 , wherein said third insulating film remains to cover said conductive film.

18. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) depositing a first insulating film over a first conductive layer formed over a main surface of a substrate;

(b) patterning said first insulating by using a mask film to form a cap film;

(c) removing said mask film;

(d) after said step (c), forming a gate electrode of a MISFET by etching said first conductive layer using said cap film as a mask;

(e) depositing a second insulating film over said gate electrode and said cap film;

(f) forming a side wall spacer on side surfaces of said gate electrode by etching said second insulating film;

(g) depositing a third insulating film over said side wall spacer and a conductive film formed over said main surface; and

(h) selectively removing said third insulating film such that at least a part of said third insulating film remains over said conductive film; and

(i) after said step (h), selectively forming a salicide layer on said gate electrode and a portion of said conductive film uncovered by said third insulating film;

wherein said cap film is removed in said step (f) by over-etching said second insulating film to etch said cap film.

19. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) depositing a first insulating film over a first conductive layer formed over a main surface of a substrate;

(b) patterning said first insulating by using a mask film to form a cap film;

(c) removing said mask film;

(d) after said step (c), forming a gate electrode of a MISFET by etching said first conductive layer using said cap film as a mask;

(e) depositing a second insulating film over said gate electrode and said cap film;

wherein said second insulating film includes the same material as said first insulating film;

(f) forming a side wall spacer on side surfaces of said gate electrode by etching said second insulating film;

(g) depositing a third insulating film over said side wall spacer and said main surface;

(h) selectively removing said third insulating film such that said third insulating film remains over at least a part of a semiconductor region formed in said substrate; and

(i) after said step (h), selectively forming a salicide layer on said gate electrode and a portion of said semiconductor region uncovered by said third insulating film;

wherein said cap film is removed in said step (f) by over-etching said second insulating film to etch said cap film.