IP Library Granted Patent US 7,500,167
Granted Patent B2
US 7,500,167 · App. 10/259,303 · Granted Mar 3, 2009

BER calculation device for calculating the BER during the decoding of an input signal

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Quick Facts
Patent No.
US 7,500,167
App. No.
10/259,303
Granted
Mar 3, 2009
Kind
B2
Abstract

In a decoder, the BER is calculated during a decode operation of the decoder. Access to decoder components for obtaining signal data for use in calculating the BER is provided during the decode operation when the components are not used by the decoder. A fetch component serves to provide the input signal to both the decoder and BER calculator at the same time. The BER calculator calculates the BER based on the output from the previous iteration. Since the decoder keep decoding the data until the final two iterations result in the same output, the calculation of the BER can be performed during the last iteration of the decoding process. An HDA early termination signal is used to confirm an accurate BER calculation.

Claims (23)

1. A decoder comprising:

an input buffer configured to receive a first input signal;

a decoding device for decoding the first input signal using an iterative process, the iterative process includes a plurality of iterations, the decoding device includes

a fetch component obtaining the first input signal from the input buffer, the fetch component configured to provide the first input signal to the decoding core and the data error calculator at the same time,

a decoder core receiving the first input signal from the fetch component and decoding the first input signal, the decoding core configured to determine that the iterative process is complete based on an nth iteration and wherein a last two consecutive iterations of the plurality of iterations have the same result, and

an output buffer for receiving the decoded first input signal; and

a re-encoder configured to re-code the decoded first input signal received from the output buffer;

a data error calculator configured to receive the first input signal and the re-encoded first input signal and calculate a transport channel bit error rate (BER) of the first input signal during the decoding of the first input signal by the core decoder, wherein the data error calculator calculates the BER based on an nth−1 iteration, such that the calculation of the BER is simultaneous with the decoding of the first input signal.

2. The decoder according to claim 1 , wherein the decoding device is configured to determine that the iterative process is complete based on the nth and nth−1 iterations.

3. The decoder according to claim 2 , further comprising a comparator configured for comparing data bits of the first input signal after each iteration and determining when the data bits of the nth and nth−1 iterations are the same.

4. The decoder according to claim 2 , wherein each iteration of the plurality of iterations is divided into half-iterations having a first and second decode processing phase, the data error calculator configured to calculate the BER during the first decode processing phase of each half-iteration.

5. The decoder according to claim 1 , wherein the decoder is a turbo decoder.

6. The decoder according to claim 1 , wherein the data error calculator comprises delay components for synchronizing the calculation of the BER of the first input signal received from the fetch component.

7. The decoder according to claim 1 , wherein the data error calculator calculates the BER during each iteration of the iterative process.

8. A method of determining a transport channel bit error rate (BER), the method comprising:

receiving a first input signal by a decoding device;

decoding the first input signal by an iterative process, the iterative process includes a plurality of iterations, and determining that the iterative process is complete based on an nth iteration and wherein a last two consecutive iterations of the plurality of iterations have the same result; and

re-encoding the decoded first input signal; and

receiving, by a data error calculator at the same time as the decoding device, the first input signal and the re-encoded first input signal and calculating the BER for the first input signal during the decoding process, wherein the step of calculating includes calculating the BER based on an nth−1 iteration, such that the calculating of the BER is simultaneous with the decode process.

9. The method according to claim 8 , wherein the step of determining comprises determining that the iterative process is complete based on the nth and nth−1 iterations.

10. The method according to claim 9 further comprising comparing data bits of the first input signal after each iteration and determining when the data bits of the nth and nth−1 iterations are the same.

11. The method according to claim 8 , wherein each iteration of the plurality of iterations is divided into half-iterations having a first and second decode processing phase, and the step of calculating comprises calculating the BER during at least one forward processing phase of each half-iteration.

12. The method according to claim 8 , wherein the data calculating step calculates the BER during each iteration of the iterative process.

Assignments (5)
SECURITY INTEREST Recorded Jun 1, 2021
From: WSOU INVESTMENTS, LLC
To: OT WSOU TERRIER HOLDINGS, LLC
Reel/Frame 056990/0081 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2018
From: ALCATEL-LUCENT USA INC.
To: WSOU INVESTMENTS, LLC
Reel/Frame 045089/0972 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2014
From: CREDIT SUISSE AG
To: ALCATEL-LUCENT USA INC.
Reel/Frame 033950/0261 →
SECURITY INTEREST Recorded Mar 7, 2013
From: ALCATEL-LUCENT USA INC.
To: CREDIT SUISSE AG
Reel/Frame 030510/0627 →
MERGER Recorded Jan 12, 2009
From: LUCENT TECHNOLOGIES INC.
To: ALCATEL-LUCENT USA INC.
Reel/Frame 022088/0352 →