Data processor with individually writable register subword locations
View Patent ↗A data processor includes program registers with individual byte-location write enables. Bypass networks allow a precision pipeline to respond to read requests by accessing a program register or pipeline stage on a byte-by-byte basis. The data processor can thus write to individual byte locations without overwriting other byte locations within the same register. The data processor has an instruction set with instructions that combine two operands and yield a one-byte result that is stored in a specified byte location of a specified result register. Eight instances of this instruction can pack eight results into a single 64-bit result register without additional packing instructions and without using a read port to read the result register before writing to it. As plural functional units can write concurrently to different subwords of the same result register, a system with four functional units can pack eight results into a result register in two instruction cycles.
1. A data processor comprising:
an instruction decoder for decoding program instructions including a first instruction calling for reading from a first program register;
an execution unit for executing said first instruction so that a read request is issued to said resister system; and
a register system including a register file with plural program registers including said first program register, a data pipeline, and bypass circuitry, said bypass circuitry responding to said read request by selecting between said first program register and said pipeline as data sources on a subword-by-subword basis.
2. A method comprising:
executing an instruction calling for a read from a first program register of a register file; and
responding to said read request by selecting between data stored in said first program register and a data pipeline on a subword-by-subword basis.