IP Library Granted Patent US 6,934,819
Granted Patent B2
US 6,934,819 · App. 10/261,682 · Granted Aug 23, 2005

Method for memory addressing in micro controller and device using the same

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Quick Facts
Patent No.
US 6,934,819
App. No.
10/261,682
Granted
Aug 23, 2005
Kind
B2
Abstract

In a memory within a micro controller, a method for addressing a page for inputting and outputting the page data on a bus. The method includes steps of producing a first control signal activated at a data update mode in which a read or write operation is executed, and determining in response to the first control signal whether the read or write operation is executed for the same page or a different page.

Claims (19)

1. A method of addressing a plurality of pages included in a memory area of a microcontroller having a read data bus and a write data bus decoupled from each other for performing a read operation and a write operation respectively, only one of the pages having a register region, comprising steps of:

updating a read data read from a page of said plurality of pages;

determining whether it is required to write back said updated read data to said page or to a different page; and

generating a first control signal according to a result of the step of determining.

2. The method as recited in claim 1 , further comprising steps of:

determining whether it is required to access the register region; and

generating a second control signal according to a result of the step of determining whether it is required to access the register region.

3. The method as recited in claim 2 , wherein only the one of the pages having the register region is accessed when the second control signal is activated.

4. The method as recited in claim 1 , wherein the plurality of pages are separately accessed at the read operation and the write operation.

5. The method as recited in claim 2 , wherein the plurality of pages are separately accessed at the read operation and the write operation.

6. A device of addressing a plurality of pages included in a memory area of a microcontroller having a read data bus and a write data bus decoupled from each other for performing a read operation and a write operation respectively, only one of the pages having a register region, comprising:

an updating means for updating a read data read from a page of said plurality of pages;

a control signal generating means for generating a first control signal according to whether it is required to write back the updated read data to said page or to a different page.

7. The device as recited in claim 6 , wherein the page selection means includes:

a read page selection means for selecting a page to read data among the plurality of pages; and

a write page selection means for selecting a page to write data among the plurality of pages.

8. The device as recited in claim 6 , further comprising:

a multiplexing means for accessing the same page at the read operation and the write operation when a second control signal is activated.

9. The device as recited in claim 7 , wherein each of the read page selections means and the write page selection means is a readable/writable storing means.