IP Library › Granted Patent US 6,627,928
Granted Patent Utility
US 6,627,928 · Confirmation No. 9779

METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT, FOR INTEGRATING AN ELECTRICALLY PROGRAMMABLE, NON-VOLATILE MEMORY AND HIGH-PERFORMANCE LOGIC CIRCUITRY IN THE SAME SEMICONDUCTOR CHIP

Patented Case View Patent ↗ View Publication ↗
⬇ PDF
 Code Description Pages PDF
2014-03-06 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2003-06-30 IFEE Issue Fee Payment (PTO-85B) 1 View
2002-10-01 TRNA Transmittal of New Application 2 View
2002-10-01 A.PE Preliminary Amendment 9 View
2002-10-01 SPEC Specification 17 View
2002-10-01 CLM Claims 4 View
2002-10-01 ABST Abstract 1 View
2002-10-01 DRW Drawings-only black and white line drawings 9 View
2002-10-01 OATH Oath or Declaration filed 3 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
Patent No.
US 6,627,928
App. No.
10/261,987
Filed
2002-10-01
Granted
2003-09-30
Pub. No.
US20030032244A1
Examiner
NHU, DAVID
Art Unit
2818
PTA
0 days