Granted Patent
Utility
US 6,605,477
· Confirmation No. 9573
INTEGRATED CIRCUIT DEVICE INCLUDING A LAYERED SUPERLATTICE MATERIAL WITH AN INTERFACE BUFFER LAYER
Inventor:
Kiyoshi Uchiyama
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-09-30 | TRNA |
Transmittal of New Application | 3 | View | |
| 2002-09-30 | ADS |
Application Data Sheet | 3 | View | |
| 2002-09-30 | A.PE |
Preliminary Amendment | 3 | View | |
| 2002-09-30 | SPEC |
Specification | 22 | View | |
| 2002-09-30 | CLM |
Claims | 7 | View | |
| 2002-09-30 | ABST |
Abstract | 1 | View | |
| 2002-09-30 | DRW |
Drawings-only black and white line drawings | 3 | View | |
| 2002-09-30 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Kiyoshi Uchiyama
Colorado Springs, CO
Attorneys & Agents of Record
Classification
USPC
438/3
H10D1/684
H10P14/69398
H10P14/6544
Prosecution
- Examiner
- HO, TU TU V
- Art Unit
- 2818
- Customer No.
- 24283
- Docket No.
- 013249.0373D1US
- Confirmation No.
- 9573
Publication
- Pub. No.
- US20030034509A1
- Pub. Date
- 2003-02-20
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2020-05-27
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Quick Facts
- Patent No.
- US 6,605,477
- App. No.
- 10/262,003
- Filed
- 2002-09-30
- Granted
- 2003-08-12
- Pub. No.
- US20030034509A1
- Examiner
- HO, TU TU V
- Art Unit
- 2818
- PTA
- 0 days
External Links