Logic analyzer having a disassembler employing symbol table information for identifying op-codes
View Patent ↗A logic analyzer according to the subject invention includes a disassembler for disassembling object code. The disassembler automates the process of locating op-code addresses by utilizing information derived from an object file corresponding to the code whose execution is being disassembled. The object file includes addresses for the starting location of op-codes corresponding to individual source code lines. When the disassembler cannot determine the correct starting location for an op-code, it uses information from the object file to obtain the address of an op-code within a specified range of interest.
1. A logic analyzer, comprising:
an acquisition arrangement for acquiring signals representative of bus transactions from a system under test;
said logic analyzer storing, analyzing, and interpreting said signals as object code statements of a program running on said system under test;
said logic analyzer storing a symbol database relating to said program running on said system under test;
said logic analyzer disassembling said object code statements into assembly code; and
said logic analyzer using said symbol database to resolve ambiguities encountered in said disassembly of said object code.
2. The logic analyzer of claim 1 , further comprising:
a display unit for displaying said assembly code; and
a data input for receiving data entered by a user for manually correcting a result of said disassembly of said object code.
3. A method for disassembling object code in a logic analyzer, comprising the steps of:
acquiring signals representative of bus transactions from a system under test;
storing, analyzing, and interpreting said signals as object code statements of a program running on said system under test;
storing a symbol database relating to said program running on said system under test;
disassembling said acquired object code statements into assembly code; and
using said symbol database to resolve ambiguities encountered during said disassembly of said object code.
4. The method of claim 3 , further comprising the steps of:
displaying said assembly code on a display screen of said logic analyzer; and
manually correcting an incorrectly disassembled line of said assembly code.
5. A logic analyzer, comprising:
an acquisition arrangement for acquiring signals representative of bus transactions from a system under test;
said system under test having a memory storing object code statements of a program running on said system under test, said logic analyzer having no access to said object code stored in said memory of said system under test;
said logic analyzer storing, analyzing, and interpreting said signals representative of bus transactions as acquired object code statements of a said program running on said system under test;
said logic analyzer storing a symbol database relating to said program running on said system under test;
said logic analyzer disassembling said acquired object code statements into assembly code; and
said logic analyzer using said symbol database to resolve ambiguities encountered in said disassembly of said acquired object code.
6. The logic analyzer of claim 5 , further comprising:
a display unit for displaying said assembly code; and
a data input for receiving data entered by a user for manually correcting a result of said disassembly of said acquired object code.
7. A method for disassembling object code in a logic analyzer, comprising the steps of:
acquiring signals representative of bus transactions from a system under test;
said system under test having a memory storing object code statements of a program running on said system under test, said logic analyzer having no access to said object code stored in said memory of said system under test;
storing, analyzing, and interpreting said signals representative of bus transactions as acquired object code statements of a program running on said system under test;
storing a symbol database relating to said program running on said system under test;
disassembling said acquired object code statements into assembly code; and
using said symbol database to resolve ambiguities encountered during said disassembly of said acquired object code.
8. The method of claim 7 , further comprising the steps of:
displaying said assembly code on a display screen of said logic analyzer; and
manually correcting an incorrectly disassembled line of said assembly code.