Package filter and combiner network

1. A transceiver front end circuit comprising:

an antenna terminal capable of being coupled to an antenna;

a first balun circuit having a single input coupled to the antenna terminal and a pair of balanced outputs coupled to a corresponding pair of balanced receiver inputs, the first balun circuit matching an input impedance of the pair of balanced receiver inputs and substantially phase shifting an input reflection coefficient of the pair of balanced receiver inputs by about 180-degrees;

a second balun circuit having a single output coupled to the antenna terminal and a pair of balanced inputs coupled to a corresponding pair of balanced transmitter outputs, the second balun circuit matching an output impedance of the pair of balanced transmitter outputs and substantially phase shifting an output reflection coefficient of the pair of balanced transmitter outputs by about 180-degrees and the first balun circuit and the second balun circuit being contained within a single package;

a first shunt switch coupled across the pair of receiver inputs, including a first transistor coupled across the pair of receiver inputs, and a means for increasing a depletion zone of the first transistor when the first shunt switch is open; and

a second shunt switch coupled across the pair of transmitter outputs, including a second transistor coupled across the pair of transmitter outputs, and a means for increasing a depletion zone of the second transistor when the second shunt switch is open.

2. The circuit of claim 1 , wherein the first transistor and the second transistor are CMOS transistors.

3. The circuit of claim 1 , wherein the single package is a low temperature co-fired ceramic (LTCC) package.

4. The circuit of claim 1 , wherein the first transistor is included in the pair of receiver inputs.

5. The circuit of claim 1 , wherein the second transistor is included in the pair of transmitter outputs.

6. The circuit of claim 1 , wherein the second transistor includes at least one output stage of a transmitter output amplifier.

7. The circuit of claim 1 , further comprising a filter including a filter input coupled to the antenna terminal, and a filter output coupled to the input of the first balun circuit and the output of the second balun circuit.

8. The circuit of claim 7 , wherein the filter is disposed within the single package.

9. The circuit of claim 7 , wherein the filter attenuates undesired signals at least about 35 decibels.

10. The circuit of claim 7 , wherein the filter is a strip line filter.

11. The circuit of claim 1 , wherein the antenna terminal has a about 50 ohm impedance.

12. The circuit of claim 11 , wherein if the first shunt switch is closed the input to the first balun circuit has an input impedance substantially greater than about 50 ohms.

13. The circuit of claim 11 , wherein if the first shunt switch is open the input to the first balun circuit has an input impedance substantially equal to about 50 ohms.

14. The circuit of claim 11 , wherein if the second shunt switch is closed the output of the second balun circuit has an impedance is substantially greater than about 50 ohms.

15. The circuit of claim 11 , wherein if the second shunt switch is open the output of the second balun circuit has an impedance substantially equal to about 50 ohms.

16. A method of switching between a receive mode and a transmit mode comprising:

coupling an input of a first balun circuit to an antenna terminal and coupling a pair of outputs of the first balun circuit to a corresponding pair of balanced receiver inputs, the first balun circuit matching an input impedance of the pair of balanced receiver inputs and substantially phase shifting an input reflection coefficient of the pair of balanced receiver inputs by about 180-degrees;

coupling an output of a second balun circuit to the antenna terminal and coupling a pair of inputs of the second balun circuit to a corresponding pair of balanced transmitter outputs, the second balun circuit matching an output impedance of the pair of balanced transmitter outputs and substantially phase shifting an output reflection coefficient of the pair of balanced transmitter outputs by about 180-degrees the first balun circuit and the second balun circuit being contained within a single package;

shorting the pair of receiver inputs during a transmit mode, wherein shorting the pair of receiver inputs includes closing a first transistor coupled across the pair of receiver inputs;

shorting the pair of transmitter outputs during a receive mode, wherein shorting the pair of transmitter outputs includes closing a second transistor coupled across the pair of transmitter outputs; and

increasing a depletion zone for the first transistor during the receive mode, and increasing a depletion zone for the second transistor during the transmit mode.

17. The method of claim 16 , wherein if the first transistor is closed the input to the first balun circuit has an impedance substantially greater to an impedance of the antenna terminal.

18. The method of claim 16 , wherein if the first transistor is open the input to the first balun circuit has an impedance substantially equal an impedance of the antenna terminal.

19. The method of claim 16 , wherein if the second transistor is closed the output of the second balun circuit has an impedance is substantially greater than an impedance of the antenna terminal.

20. The method of claim 16 , wherein if the second transistor is open the output of the second balun circuit has an impedance substantially equal to an impedance of the antenna terminal.

21. The method of claim 16 , wherein the first transistor and the second transistor are CMOS transistors.

22. The method of claim 16 , further comprising filtering a signal between the antenna terminal and a second terminal, the second terminal being coupled to the input of the first balun circuit and the output of the second balun circuit.

23. The method of claim 22 , wherein the filter attenuates undesired signals at least about 35 decibels.