Computer system supporting both dirty-shared and non-dirty-shared data processing entities
View Patent ↗A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer system may include a portion of shared memory that stores data in terms of memory blocks. Upon receiving a snoop read requesting shared access to a memory block held in a dirty state, a dirty-shared processor sends a copy of the memory block to the originator of the snoop read and retains a valid a copy of the block in its cache. Non dirty-shared processors additionally write the block back to main memory in response to snoop reads and may also send a copy to the originator. Until the write back is completed at main memory or another processor is granted write access to the block, the dirty-shared and non dirty-shared processors preferably continue to satisfy sub-sequent snoop reads targeting the memory block.
1. A computer system comprising:
a plurality of processors; and
a main memory coupled to the plurality of processors by an interconnect fabric, the main memory organized to store data in terms of memory blocks at least one or more of which are shared by the plurality of processors, wherein,
the processors store memory blocks to which they have write access in a dirty state,
at least one processor operates in a dirty-shared mode such that the at least one dirty-shared processor is configured to share memory blocks that the dirty-shared processor holds in the dirty state with one or more other processors, and
at least one processor operates in a non dirty-shared mode such that the at least one non dirty-shared processor is precluded from sharing memory blocks that the non dirty-shared processor holds in the dirty state with one or more other processors.
2. The computer system of claim 1 wherein the at least one non dirty-shared processor responds to a first snoop read targeting a dirty memory block by writing the dirty memory block back to the main memory.
3. The computer system of claim 2 wherein
the first snoop read is initiated by a first source processor, and
the at least one non dirty-shared processor further responds to the first snoop read by sending a copy of the dirty memory block to the first source processor.
4. The computer system of claim 3 wherein the at least one non dirty-shared processor responds to a second snoop read initiated by a second source processor by sending a copy of the dirty memory block to the second source processor, provided that the dirty memory block remains valid.
5. The computer system of claim 4 wherein the second snoop read is issued by the main memory before the dirty memory block is written back thereto.
6. The computer system of claim 2 wherein the at least one dirty-shared processor responds to a second snoop read initiated by a source processor targeting a dirty memory block by sending a copy of the dirty memory block to the source processor without writing the dirty memory block back to the main memory.
7. The computer system of claim 1 further comprising one or more directories for use in maintaining coherence of the memory blocks, the one or more directories having an entry for each memory block, each directory entry including an owner field for specifying an owner of the memory block, and a writer field for specifying the last processor to have written the memory block back to the main memory.
8. The computer system of claim 7 wherein each directory entry further includes a sharer list field for specifying which processors have a shared copy of the respective memory block.
9. The computer system of claim 7 wherein the processors and the main memory cooperate in the execution of a single cache coherency protocol.
10. The computer system of claim 7 wherein
the main memory is formed from a plurality of memory subsystems, and
the directory is distributed across the plurality of memory subsystems.
11. The computer system of claim 7 wherein the directory is free from maintaining one or more transient states for the memory blocks.
12. A method for use by a computer system having a plurality of processors and a main memory configured to store data in terms of memory blocks accessible by the plurality of processors through an interconnect fabric, the method comprising the steps of:
storing a memory block at a processor that has write access to the memory block in a dirty state;
responding to a snoop read received at a first processor that targets a dirty memory block by writing the dirty memory block from the first processor back to the main memory; and
responding to a snoop read initiated by a source processor and received at a second processor that targets a dirty memory block by sending a copy of the dirty memory block from the second processor to the source processor without writing the dirty memory block back to the main memory.
13. The method of claim 12 wherein the snoop read received at the first processor is initiated by a second source processor, the method further comprising the step of further responding to the snoop read received at the first processor by sending a copy of the dirty memory block from the first processor to the second source processor.
14. The method of claim 12 further comprising the step of providing at least one directory for use in maintaining coherence of the memory blocks configured at the main memory, the directory having, for each memory block, an owner field specifying the owner of the respective memory block, a sharer list specifying the processors that have a shared copy of the respective memory block, and a writer field specifying the last processor to have written the respective memory block back to the main memory.