Multimode controller for intelligent and “dumb” flash cards
View Patent ↗A controller chip for coupling a computer system with a flash storage system is disclosed. The controller chip comprises an interface mechanism for determining whether the Flash storage system includes a controller and an adapter for providing the appropriate interface to the computer system to allow the computer system to communicate with the Flash storage system. In a preferred embodiment, the flash storage system comprising at least a portion of a medium ID section; and a flash section, wherein the medium ID section contains specifications of the medium ID. Through the use of this system a plurality of different adapters and a flash storage system can be managed while utilizing the same hardware components.
1. A controller chip comprising:
an interface mechanism capable of receiving flash storage systems with controllers and flash storage systems without controllers, a flash storage system to be coupled to a computer system;
a detector to determine whether the flash storage system includes a controller for error correction; and
a flash adapter to interface the computer system with the flash storage system, the flash adapter comprising:
a first interface to be coupled to the computer system;
a second of interface to be coupled to the flash storage system, wherein the flash storage system comprises a flash section and at least a medium ID; and
a firmware in the flash adapter, in an event where the flash storage system does not have a controller for error correction, to perform operations to manage error correction of the flash section in the flash storage system that is coupled to the flash adapter by the second interface, including bad block mapping of the flash section.
2. The controller chip of claim 1 , wherein the medium ID contains specifications of the flash storage system.
3. The controller chip of claim 2 , wherein the flash adapter further comprises at least another portion of the medium ID.
4. The controller chip of claim 2 , wherein the medium ID comprises a pull-up resistor and a pull-down resistor.
5. The controller chip of claim 2 , wherein the medium ID further comprises a voltage divider.
6. The controller chip of claim 2 , wherein the medium ID further comprises an EEPROM device to store the specifications of the flash storage system.
7. A method comprising:
using a controller chip to interface a flash storage system with or without a controller to a computing device, the controller chip comprising a flash adapter, wherein the flash storage system comprises a flash section and at least a medium ID;
determining whether the flash storage system includes a controller for error correction; and
in an event where the flash storage system does not have a controller for error correction, using firmware in the flash adapter to perform operations to manage error correction of the flash section, including bad block mapping of the flash section in the flash storage system that is coupled to the flash adapter section.
8. The method of claim 7 , further comprising: storing specifications of the flash storage system in the medium ID.
9. The method of claim 7 , further comprising updating the specifications in the medium ID during bad block mapping of the flash section, wherein the medium ID comprises one or more EEPROM devices to store the specifications.
10. The method of claim 7 , further comprising examining the medium ID to identify a type of the flash storage system, wherein the medium ID comprises at least one of a pull-up resistor, a pull-down resistor, and a voltage divider.
11. A system comprising:
a computing device;
a flash storage system comprising a flash section and at least a portion of a medium ID; and
a controller chip coupled between the computing device and the flash storage system to interface the flash storage system to the computing device, the controller chip comprising an interface mechanism capable of receiving flash storage systems with controller and controllerless flash storage systems, a detector to determine whether the flash storage system includes a controller for error correction and a flash adapter which comprises firmware to perform, in an event where the flash storage system does not have a controller for error correction, operations to manage error correction of the flash section, including bad block mapping of the flash section in the flash storage system that is coupled to the flash adapter section.
12. The system of claim 11 , wherein the medium ID contains specifications of the flash storage system.
13. The system of claim 12 , wherein the flash adapter further comprises at least another portion of the medium ID.
14. The system of claim 12 , wherein the medium ID comprises a pull-up resistor and a pull-down resistor.
15. The system of claim 12 , wherein the medium ID comprises a voltage divider.
16. The system of claim 12 , wherein the medium ID comprises an EEPROM device to store the specifications of the flash storage system.
17. The controller chip of claim 1 , wherein the flash adapter further comprises a plurality of interfaces for receiving a plurality of flash storage systems.
18. The controller chip of claim 1 , wherein the bad block mapping includes addressing a new boot sector to allow use of the storage system with a bad boot sector.
19. The method of claim 7 , wherein the flash adapter further comprises a plurality of interfaces for receiving a plurality of flash storage systems.
20. The method of claim 7 , wherein the bad block mapping includes addressing a new boot sector to allow use of the storage system with a bad boot sector.
21. The system of claim 11 , wherein the flash adapter further comprises a plurality of interfaces for receiving a plurality of flash storage systems.
22. The controller chip of claim 11 , wherein the bad block mapping includes addressing a new boot sector to allow use of the storage system with a bad boot sector.