Method to test power distribution system
View Patent ↗A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether the core power distribution system functions is acceptable at a particular frequency.
1. A method for testing a core power distribution system for an integrated circuit chip comprising:
arranging a plurality of experiments for an integrated circuit chip, the arranging the plurality of experiments for the integrated circuit chip including progressively depopulating pins of the integrated circuit chip;
performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
generating a schmoo diagram for each of the plurality of experiments; and
analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
2. The method for testing a core power distribution system of claim 1 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.
3. The method for testing a core power distribution system of claim 1 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.
4. The method for testing a core power distribution system of claim 1 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.
5. The method for testing a core power distribution system of claim 1 further comprising:
repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
generating a schmoo diagram for each of the repeated plurality of experiments; and
analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
6. A method for testing a core power distribution system for an integrated circuit chip comprising:
arranging a plurality of experiments for an integrated circuit chip;
performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
generating a schmoo diagram for each of the plurality of experiments; and
analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the arranging a plurality of experiments for an integrated circuit chip includes at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.
7. A system for testing a core power distribution system for an integrated circuit chip comprising:
means for arranging a plurality of experiments for an integrated circuit chip, the means for arranging the plurality of experiments for the integrated circuit chip includes progressively depopulating pins of the integrated circuit chip;
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
8. The system for testing a core power distribution system of claim 7 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.
9. The system for testing a core power distribution system of claim 7 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.
10. The system for testing a core power distribution system of claim 7 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.
11. The system for testing a core power distribution system of claim 7 further comprising:
means for repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the repeated plurality of experiments; and,
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
12. A system for testing a core power distribution system for an integrated circuit chip comprising:
means for arranging a plurality of experiments for an integrated circuit chip;
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the means for arranging a plurality of experiments for an integrated circuit chip includes at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.
13. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.
14. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.
15. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.
16. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the plurality of experiments for an integrated circuit chip include at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.
17. The apparatus for testing a core power distribution system of claim 16 further comprising:
means for repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the repeated plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.