Asynchronous control circuit with symmetric forward and reverse latencies

1. A control queue for an asynchronous circuit, comprising:

a number of control modules coupled together linearly to form the control queue, including a prior module, a present module and a next module;

wherein the present module is configured to receive one or more forward-going inputs from the prior module and one or more reverse-going inputs from the next module;

wherein the present module is configured to asynchronously generate one or more forward-going outputs to the next module and one or more reverse-going outputs to the prior module; and

wherein the latency of forward-going signals through the control queue is equal to the latency of reverse-going signals through the control queue.

2. The control queue of claim 1 , wherein the present module is configured to asynchronously perform a decision-wait function on the one or more forward-going inputs received from the prior module and the one or more reserve-going inputs received from the next module;

wherein the decision-wait function asynchronously generates the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module when sufficient of the inputs to the decision-wait function are asserted.

3. The control queue of claim 1 , wherein the present module is configured to asynchronously perform a join function on the one or more forward-going inputs received from the prior module and the one or more reverse-going inputs received from the next module;

wherein the join function asynchronously generates the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module when sufficient of the inputs to the join function are asserted.

4. The control queue of claim 1 , wherein the control signals between modules alternate in polarity, so that an assertion of a forward-going signal is encoded as a high voltage between the prior module and the present module, and is encoded as a low voltage between that present module and the next module.

5. The control queue of claim 1 , wherein successive modules in the control queue alternate between 2-4 GasP modules and 4-2 GasP modules.

6. The control queue of claim 1 , further comprising a number of successive stages of latches that operate under control of corresponding control modules in the control queue.

7. The control queue of claim 1 , wherein the latency of forward-going control signals and reverse going control signals through the control queue are each an odd number of gate delays.

8. The control queue of claim 1 , wherein the average latency of forward-going control signals and reverse going control signals through the control queue are each three gate delays.

9. A method for operating a control queue for an asynchronous circuit, wherein a number of control modules are coupled together linearly to form the control queue, wherein the control queue includes a prior module, a present module and a next module, the method comprising:

receiving one or more forward-going inputs from the prior module and one or more reverse-going inputs from the next module at the present module; and

generating one or more forward-going outputs to the next module and one or more reverse-going outputs to the prior module from the present module;

wherein the average latency of forward-going signals through the control queue is equal to the latency of reverse-going signals through the control queue.

10. The method of claim 9 , wherein generating the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module involves:

asynchronously performing a decision-wait function on the one or more forward-going inputs received from the prior module and the one or more reserve-going inputs received from the next module; and

asynchronously generating the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module when sufficient of the inputs to the decision-wait function are asserted.

11. The method of claim 9 , wherein generating the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module involves:

asynchronously performing a join function on the one or more forward-going inputs received from the prior module and the one or more reverse-going inputs received from the next module; and

asynchronously generating the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module when sufficient of the inputs to the join function are asserted.

12. The method of claim 9 , wherein the control signals between modules in polarity, so that an assertion of a forward-going signal is encoded as a high voltage between the prior module and the present module, and is encoded as a low voltage between that present module and the next module.

13. The method of claim 9 , wherein successive modules in the control queue alternate between 2-4 GasP modules and 4-2 GasP modules.

14. The method of claim 9 , wherein a number of successive stages of latches operate under control of corresponding control modules in the control queue.

15. The method of claim 9 , wherein the latency of forward-going control signals and reverse going control signals through the control queue are each an odd number of gate delays.

16. The method of claim 9 , wherein the average latency of forward-going control signals and reverse going control signals through the control queue are each three gate delays.

17. A computer system containing asynchronous circuitry, comprising:

a processor;

a memory;

asynchronous circuitry; and

a control queue within the asynchronous circuitry; wherein the control queue includes a number of control modules coupled together linearly to form the control queue, including a prior module, a present module and a next module;

wherein the present module is configured to receive one or more forward-going inputs from the prior module and one or more reverse-going inputs from the next module;

wherein the present module is configured to asynchronously generate one or more forward-going outputs to the next module and one or more reverse-going outputs to the prior module; and

wherein the latency of forward-going signals through the control queue is equal to the latency of reverse-going signals through the control queue.

18. The computer system of claim 17 , wherein the present module is configured to asynchronously perform a decision-wait function on the one or more forward-going inputs received from the prior module and the one or more reserve-going inputs received from the next module;

wherein the decision-wait function asynchronously generates the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module when sufficient of the inputs to the decision-wait function are asserted.

19. The computer system of claim 17 , wherein the present module is configured to asynchronously perform a join function on the one or more forward-going inputs received from the prior module and the one or more reverse-going inputs received from the next module;

wherein the join function asynchronously generates the one or more forward-going outputs to the next module and the one or more reverse-going outputs to the prior module when sufficient of the inputs to the join function are asserted.

20. The computer system of claim 17 , wherein the control signals between modules alternate in polarity, so that an assertion of a forward-going signal is encoded as a high voltage between the prior module and the present module, and is encoded as a low voltage between that present module and the next module.

21. The computer system of claim 17 , wherein successive modules in the control queue alternate between 2-4 GasP modules and 4-2 GasP modules.

22. The computer system of claim 17 , further comprising a number of successive stages of latches that operate under control of corresponding control modules in the control queue.

23. The computer system of claim 17 , wherein the latency of forward-going control signals and reverse going control signals through the control queue are each an odd number of gate delays.

24. The computer system of claim 17 , wherein the average latency of forward-going control signals and reverse going control signals through the control queue are each three gate delays.