Verification of memory operations by multiple processors to a shared memory
View Patent ↗A method and apparatus for testing cache coherency in a multiprocessor data processing arrangement. Selected values are written to memory by a plurality of threads, and consistency of the values in the memory with the values written by the plurality of threads is verified. Performance characteristics of the data processing system are measured while writing the values, and in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads are selectively adjusted.
1. A computer-implemented method for testing memory operations in a multiprocessor data processing arrangement, comprising:
logically partitioning a selected portion of memory into partitions respectively associated with a plurality of threads;
assigning disjoint sets of values to the threads for writing to the associated partitions;
wherein each partition is defined by a beginning offset, an ending offset, a contiguous byte count, and an increment value, the beginning offset being a position in the selected portion of memory, relative to a starting address of the portion of memory, at which the partition begins, the ending offset being a position in the selected portion of memory, relative to the starting address of the portion of memory, at which the partition ends, the contiguous byte count being a number of consecutively addressed bytes that belong to the partition, and the increment value being a number of bytes that are not in the partition and that separate two sets of contiguously addressed bytes of the partition;
writing the sets of values to memory by the plurality of threads;
verifying that values in the memory are consistent with the values written by the plurality of threads;
measuring performance characteristics of the data processing system while writing the values; and
selectively adjusting, in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads.
2. The method of claim 1 , further comprising assigning the threads to execute on different processors.
3. The method of claim 1 , further comprising varying the number of threads that are active in selected time intervals.
4. The method of claim 1 , wherein each partition includes contiguously addressable memory locations.
5. The method of claim 1 , wherein each partition includes non-contiguously addressable memory locations.
6. The method of claim 1 , wherein at least one partition includes contiguously addressable memory locations.
7. The method of claim 1 , wherein at least one partition includes non-contiguously addressable memory locations.
8. A computer-implemented method for testing memory operations in a multiprocessor data processing arrangement, comprising:
allocating a portion of memory of selected size;
dividing the portion of memory into a plurality of partitions in accordance with a partition scheme;
wherein each partition is defined by a beginning offset, an ending offset, a contiguous byte count, and an increment value, the beginning offset being a position in the selected portion of memory, relative to a starting address of the portion of memory, at which the partition begins, the ending offset being a position in the selected portion of memory, relative to the starting address of the portion of memory, at which the partition ends, the contiguous byte count being a number of consecutively addressed bytes that belong to the partition, and the increment value being a number of bytes that are not in the partition and that separate two sets of contiguously addressed bytes of the partition;
distributing a plurality of threads for execution on a plurality of processors;
establishing a target data set representing target performance characteristics;
writing assigned values by each thread to an associated one of the partitions, wherein each thread is associated with no more than one partition, and the values written by a thread are unique relative to values written by other ones of the threads;
verifying that contents of locations in the portion of memory are consistent with associated partitions and assigned values of the threads;
measuring performance characteristics of the data processing system while writing the values; and
selectively adjusting the partition scheme in response to the performance characteristics relative to the target data set.
9. The method of claim 8 , further comprising:
selectively adjusting the number of threads executing on the processors in response to the performance characteristics relative to the target data set.
10. The method of claim 8 , further comprising:
selectively adjusting the size of the portion of memory in response to the performance characteristics relative to the target data set.
11. The method of claim 8 , wherein each partition includes contiguously addressable memory locations.
12. The method of claim 8 , wherein each partition includes non-contiguously addressable memory locations.
13. The method of claim 8 , wherein at least one partition includes contiguously addressable memory locations.
14. The method of claim 8 , wherein at least one partition includes non-contiguously addressable memory locations.
15. An apparatus for testing memory operations in a multiprocessor data processing arrangement, comprising:
means for logically partitioning a selected portion of memory into partitions respectively associated with a plurality of threads;
means for assigning disjoint sets of values to the threads for writing to the associated partitions;
wherein each partition is defined by a beginning offset, an ending offset, a contiguous byte count, and an increment value, the beginning offset being a position in the selected portion of memory, relative to a starting address of the portion of memory, at which the partition begins, the ending offset being a position in the selected portion of memory, relative to the starting address of the portion of memory, at which the partition ends, the contiguous byte count being a number of consecutively addressed bytes that belong to the partition, and the increment value being a number of bytes that are not in the partition and that separate two sets of contiguously addressed bytes of the partition;
means for writing the sets of values to memory by the plurality of threads;
means for verifying that values in the memory are consistent with the values written by the plurality of threads;
means for measuring performance characteristics of the data processing system while writing the values; and
means for selectively adjusting, in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads.
16. A computer-implemented method for testing memory operations in a multiprocessor data processing arrangement, comprising:
logically partitioning a selected portion of memory into partitions respectively associated with a plurality of threads;
assigning disjoint sets of values to the threads for writing to the associated partitions;
wherein each partition is defined by a beginning offset, an ending offset, a contiguous byte count, and an increment value, the beginning offset being a position in the selected portion of memory, relative to a starting address of the portion of memory, at which the partition begins, the ending offset being a position in the selected portion of memory, relative to the starting address of the portion of memory, at which the partition ends, the contiguous byte count being a number of consecutively addressed bytes that belong to the partition, and the increment value being a number of bytes that are not in the partition and that separate two sets of contiguously addressed bytes of the partition;
assigning the threads to execute on different processors;
writing the sets of values to memory by the plurality of threads;
verifying that values in the memory are consistent with the values written by the plurality of threads.
17. The method of claim 16 , further comprising varying the number of threads that are active in selected time intervals.
18. The method of claim 16 , wherein each partition includes contiguously addressable memory locations.
19. The method of claim 16 , wherein each partition includes non-contiguously addressable memory locations.
20. The method of claim 16 , wherein at least one partition includes contiguously addressable memory locations.
21. The method of claim 16 , wherein at least one partition includes non-contiguously addressable memory locations.