Multi-threshold MIS integrated circuit device and circuit design method thereof
View Patent ↗On a chip 50 A, disposed are macro cell 20 A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51 G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20 A, and has a drain region 51 D connected to VDD pads 60 and 61 for external connection, the gate line 51 G connected to an I/O cell 73 and a source region 51 S connected to a VDD terminal of the macro cell 20 A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.
1. A multi-threshold MIS integrated circuit device comprising:
a first macro, including a first internal circuit and a first virtual power supply line connected to the first internal circuit, the first internal circuit including a MIS transistor having a first threshold voltage; and
a first leak-current-shielding MIS transistor cell, having a first gate line connected to a first power control line, having a longitudinal direction coincident with the first gate line, being formed along a side of a macro frame of the first macro, having a second threshold voltage different from the first threshold voltage, having a current path whose one end and another end are connected to a first power supply line and the first virtual power supply line, respectively,
wherein the first macro and the first leak-current-shielding MIS transistor cell are formed on a substrate.
2. The multi-threshold MIS integrated circuit device according to claim 1 , wherein the first MIS transistor cell has a predetermined size, a plurality of the first MIS transistor cells are disposed along a side of the macro frame of the first macro, and gate lines of each adjacent pair of the first MIS transistor cells are connected to each other.
3. The multi-threshold MIS integrated circuit device according to claim 1 , wherein the macro frame of the first macro is rectangular in shape, and the first MIS transistor cells are disposed along at least two sides of the macro frame.
4. The multi-threshold MIS integrated circuit device according to claim 1 , wherein the first macro further includes a second virtual power supply line connected to the first internal circuit,
the device further comprising:
a second leak-current-shielding MIS transistor cell, having a second gate line connected to a second power control line, having a longitudinal direction coincident with the second gate line, being formed along a side of a macro frame of the first macro, having a third threshold voltage different from the first threshold voltage, having a current path whose one end and another end are connected to a second power supply line and the second virtual power supply line, respectively.
5. The multi-threshold MIS integrated circuit device according to claim 4 , wherein the second power supply line is connected to a pad formed on the substrate, the pad being for external connection.
6. The multi-threshold MIS integrated circuit device according to claim 1 , wherein the first power supply line is connected to a pad formed on the substrate, the pad being for external connection.
7. The multi-threshold MIS integrated circuit device according to claim 1 , wherein the first power supply line has a power supply ring formed in a peripheral of one including the first macro and the first MIS transistor cell.
8. The multi-threshold MIS integrated circuit device according to claim 1 , wherein the first power control line is connected to a pad formed on the substrate, the pad being for external connection.
9. The multi-threshold MIS integrated circuit device according to claim 1 , further comprising: a second macro, including a second internal circuit for supplying a control signal to the first power control line, including the first power supply line connected to both the second internal circuit and a pad formed on the substrate, the pad being for external connection.