Digital filter for reducing voltage peaks
The present invention relates to a digital filter suitable for receiving a digital input signal (INPUT(G)) comprising a voltage peak also known as glitch (G). It is characterized in that it comprises: a delay line (T) adapted to produce a delayed digital input signal (INPUT(G)+Δt), rising edge (PD) and falling edge (ND) detectors adapted to produce rising (P) and falling (N) edge indicator signals respectively from the delayed digital input signal (INPUT(G)+Δt), first (M 1 ) and second (M 2 ) mixing means adapted to produce rising (P′) and falling (N′) edge filter indicator signals respectively from said digital input signal (INPUT(G)) and said rising (P) and falling (N) edge indicator signals respectively, third mixing means (M 3 ) adapted to produce a digital output signal (OUTPUT) without a glitch from the rising edge filter indicator signal (P′) and from the falling edge filter indicator signal (N′).
1. A digital filter suitable for receiving a digital input signal (INPUT(G)), comprising a rising edge detector (PD), a falling edge detector (ND), a delay line (T) adapted to delay said digital input signal (INPUT(G)) and to produce a delayed digital input signal (INPUT(G)+Δt), said digital input signal (INPUT(G)) comprising a voltage peak also known as glitch, wherein:
the rising edge detector (PD) is adapted to produce a rising edge indicator signal (P) from the delayed digital input signal (INPUT(G)+Δt),
the falling edge detector (ND) is adapted to produce a falling edge indicator signal (N) from the delayed digital input signal (INPUT(G)+Δt),
first mixing means (M 1 ) adapted to produce a rising edge filter indicator signal (P′) from said digital input signal (INPUT(G)) and said rising edge indicator signal (P),
second mixing means (M 2 ) adapted to produce a falling edge filter indicator signal (N′) from said digital input signal (INPUT(G)) and said falling edge indicator signal (N), and
third mixing means (M 3 ) adapted to produce a digital output signal (OUTPUT) without a glitch, having a duration no greater than delay Δt, from the rising edge filter indicator signal (P′) and the falling edge filter indicator signal (N′).
2. A digital filter as claimed in claim 1 , wherein the first mixing means (M 1 ) fulfill a logic AND function, and the second filtering means (M 2 ) fulfill an inverting function along with a logic AND function.
3. A digital filter as claimed in claim 1 , wherein the third filtering means (M 3 ) is an RS flip-flop.
4. A digital filter as claimed in claim 1 , wherein the rising edge (PD) and falling edge (ND) detectors are D flip-flops having a connection of inverters (INV) from an output (Q) to a reset input (R).
5. A method of filtering a digital signal (INPUT(G)) comprising a glitch, the method comprises the steps of:
delaying said digital input signal (INPUT(G)) and producing a delayed digital input signal (INPUT(G)+Δt),
detecting a rising edge coming from the delayed digital input signal (INPUT(G)+Δt) and producing a rising edge indicator signal (P),
detecting a falling edge coming from the delayed digital input signal (INPUT(G)+Δt) and producing a falling edge indicator signal (N),
producing a rising edge filter indicator signal (P′) from said digital input signal (INPUT(G)) and said rising edge indicator signal (P),
producing a falling edge filter indicator signal (N′) from said digital input signal (INPUT(G)) and said falling edge indicator signal (N), and
producing a digital output signal (OUTPUT) without a glitch, having a duration no greater than delay Δt, from the rising edge filter indicator signal (P′) and the falling edge filter indicator signal (N′).
6. A module (RTC) comprising a squared signal generator (CLK) transforming an analog signal into a digital input signal (INPUT(G)), comprises:
a digital filter as claimed in claim 1 suitable for receiving said digital input signal (INPUT(G)).
7. A portable telephone comprising a module (RTC) as claimed in claim 6 .