EDGE modulator
View Patent ↗Circuits and methods for modulators that receive symbols, and provide I (incident, or in-phase) and Q (quadrature) component values from a look-up table for subsequent filtering and digital-to-analog conversion. The I and Q component values depend on frequency correction and time index signals such that operating frequency differences between a handset and base station are compensated for, and the transmitted symbols are continuously phase shifted by 3π/8 radians.
1. A method of transmitting a wireless, signal comprising:
generating a time index signal;
receiving a frequency offset signal;
accumulating the frequency offset signal;
dividing the accumulated frequency offset signal;
acquiring at least one symbol to be transmitted wirelessly, said at least one symbol being separate from said time index signal and said frequency offset signal; and
determining an in-phase component value and a quadrature component value corresponding to the acquired at least one symbol, using each of the time index signal, the divided accumulated frequency offset signal, and the acquired at least one symbol.
2. The method of claim 1 , wherein the time index signal is generated using a counter.
3. The method of claim 2 , wherein the frequency offset signal is provided by a receiver circuit.
4. The method of claim 2 , wherein the dividing the accumulated frequency offset signal is done by right shifting the accumulated frequency offset signal by 6 bits.
5. The method of claim 2 , wherein the determining an in-phase component value and a quadrature component value using the time index signal, the divided accumulated frequency offset signal, and the acquired symbol is done using a look-up table.
6. The method of claim 5 , wherein the look-up table comprises 128 entries.
7. The method of claim 1 , wherein the in-phase component and quadrature components are digitally filtered.
8. The method of claim 7 , wherein the digitally filtered in-phase and quadrature components are converted to analog signals, and wherein the analog signals are low-pass filtered.
9. An integrated circuit including a transceiver, the transceiver comprising:
a receiver; and
a transmitter coupled to the receiver, the transmitter including a modulator comprising:
a counter;
a summer coupled to an output of the counter;
a divider coupled to an output of the summer; and
a look-up table coupled to an output of the divider and the output of the counter,
wherein the lookup table receives input symbols to be wirelessly transmitted, and provides in-phase and quadrature component values corresponding to the received input symbols, said input symbols being separate from said output of the divider and said output of the counter.
10. The integrated circuit of claim 9 , wherein the receiver generates a frequency offset signal, and the frequency offset signal is accumulated by the summer.
11. The integrated circuit of claim 10 , wherein the counter provides a time index signal.
12. The integrated circuit of claim 9 , wherein each input symbol is one of eight symbols.
13. The integrated circuit of claim 12 , wherein the time index signal changes a corresponding location in the look-up table such that each symbol is phase shifted by 3π/8 radians.
14. The integrated circuit of claim 9 , comprising:
a digital filter coupled to an output of the loop-up table;
a digital-to-analog converter coupled to an output of the digital filter; and
a low-pass filter coupled an output of the digital-to-analog converter.
15. A modulator of a transmitter, the modulator comprising:
a counter configured to provide a time index signal;
a summer configured to receive a frequency offset signal and the time index signal and provide a cumulative phase error;
a divider configured to receive the cumulative phase error and provide a phase offset index; and
a look-up table configured to receive the phase offset index and the time index, and further configured to receive an input symbol, and provide in-phase and quadrature component values corresponding to the received input symbol, said input symbol being separate from said phase offset index and said time index.
16. The modulator of claim 15 , wherein the counter counts to a first number, the divider divides by a second number, and the first number is an integral multiple of the second number.
17. The modulator of claim 16 , wherein the counter counts to 512 and the divider divides by 64.
18. The modulator of claim 16 , wherein the input symbol comprises three bits of information.
19. The modulator of claim 15 , wherein the in-phase and quadrature component values are provided to a digital filter.
20. The modulator of claim 15 , wherein the look-up table comprises 128 entries.