Method and apparatus for a packet classifier

1. A method for efficiently classifying packets for a multi-processor/mutli-thread environment, comprising:

receiving a packet;

extracting header information from the received packet;

calculating a first hash value;

determining a field of interest in a lookup table from the first hash value;

calculating a second hash value;

comparing the second hash value to stored hash values in the field of interest of the lookup table to determine a match between the second hash value and one of the values in the field of interest of the lookup table; and

if there is a match, transmitting the received packet to a processor corresponding to the one of the values in the row location of the lookup table.

2. The method of claim 1 , wherein the second hash value has a smaller bit size than the extracted header information.

3. The method of claim 1 , wherein the field of interest is a row of the lookup table.

4. The method of claim 1 , wherein the method operation of transmitting the received packet to a processor corresponding to the one of the values in the field of interest of the lookup table includes,

transmitting the received packet to a queue associated with the processor.

5. The method of claim 1 , wherein the method operation of extracting header information from the received packet includes,

defining a key from fields of a header of the received packet.

6. The method of claim 5 , wherein the fields are located in layers 2–4 of the packet header.

7. The method of claim 1 , further including:

if there is not a match, performing a round robin operation to determine which processor to transmit the received packet to.

8. A method for performing optimistic hash matching, comprising:

defining a lookup table having a plurality of values stored therein, each of the plurality of values being associated with at least one processor;

receiving a packet;

extracting a key from the packet;

calculating a first hash value and a second hash value from the key;

identifying a field of interest within the lookup table corresponding to the first hash value;

comparing the second hash value to values within the field of interest to identify a match between the second hash value and one of the values within the field of interest; and

sending the received packet to a processor corresponding to the one of the values within the field of interest.

9. The method of claim 8 , wherein the first and the second hash values are calculated through different hash algorithms.

10. The method of claim 9 , wherein the plurality of values in the lookup table and the second hash value are derived through a common hash algorithm.

11. The method of claim 8 , further including:

accessing code associated with the one of the values within the field of interest to determine an address of a processor assigned to the received packet.

12. The method of claim 8 wherein the method operation of sending the packet to a processor corresponding to the one of the values within the field of interest includes,

holding the packet in a queue associated with the processor.

13. The method of claim 8 further including:

if there is not a match between the second hash value and one of the values within the field of interest, performing a round robin operation to identify one of a plurality of processors to send the packet to.

14. A network interface card, comprising:

circuitry for receiving a packet;

packet classifier circuitry, the packet classifier circuitry configured to calculate a first hash value and a second hash value from fields of a packet header of the received packet, the first hash value indicating a field of interest associated with a lookup table in communication with the network interface card, the second hash value matching a value within the field of interest to identify a processor assigned to the packet; and

circuitry for transmitting the packet to a queue associated with the processor assigned to the packet.

15. The network interface card of claim 14 , wherein the network interface card is on a multi-processor chip.

16. The network interface card of claim 15 , wherein the multi-processor chip is contained within a server computer.

17. A system for efficiently classifying packets in a multicore/multithread environment, comprising:

a multi-processor chip in communication with a semiconductor chip storing data, the multi-processor chip including,

a plurality of processor cores;

a network interface card (NIC) for receiving a packet from a network; the NIC having packet classifier circuitry, the packet classifier circuitry configured to calculate a first hash value and a second hash value from a packet header of the packet, the first hash value indicating a field of interest in a table, the second hash value identifying data at a location in the field of interest, the data indicating one of the plurality of processor cores for the packet to be sent to; and

a semiconductor chip configured to store data associated with the table, the semiconductor chip in communication with the multi-processor chip.

18. The system of claim 17 , wherein the table is stored in a fast cycle dynamic random access memory (FCDRAM).

19. The system of claim 17 , wherein the system is a server computer.

20. The system of claim 17 , further including:

a set of queues corresponding to the processor cores, such that one queue corresponds to one processor core.