DRAM power management

1. A computing system comprising:

a processor;

a memory system, that includes at least one DRAM module;

a DRAM controller, wherein the DRAM controller includes:

logic for selecting a memory access rate, the selected memory access rate corresponding to a desired average memory power consumption rate;

logic for starting a first time interval as a current time interval;

logic for accessing a memory system;

logic for determining if the memory access rate has not been exceeded, then applying the access to the memory system; and

logic for determining if the memory access rate has been exceeded, then:

logic for delaying the access until the current time interval has expired;

logic for starting a subsequent time interval as the current time interval; and

logic for applying the access to the memory system; and

a bus that couples the memory system, the processor and the DRAM controller.

2. The system of claim 1 , wherein the DRAM controller includes a state machine.

3. The system of claim 1 , further comprising a power supply for the memory system.

4. The system of claim 3 , wherein the length for the current time interval is less than a regulation time constant of the power supply for the memory system.

5. The system of claim 3 , wherein the length for the current time interval is equal to about 10 microseconds.

6. The system of claim 1 , wherein the desired memory power consumption rate is equal to about 66 percent of a maximum power consumption of the at least one DRAM module.

7. The system of claim 1 , wherein the desired memory power consumption rate is equal to about 9 watts for each of the at least one DRAM module.

8. The system of claim 1 , wherein the processor includes the DRAM controller.

9. A method for limiting power consumption of a computer memory system comprising:

selecting a memory access rate, the selected memory access rate corresponds to a desired average memory power consumption rate;

starting a first time interval as a current time interval;

accessing a memory system;

if the memory access rate has not been exceeded, then applying the access to the memory system; and

if the memory access rate has been exceeded, then:

delaying the access until the current time interval has expired;

starting a subsequent time interval as the current time interval; and

applying the access to the memory system.

10. The method of claim 9 , wherein accessing the memory system can include:

determining if the current time interval has expired, if the current time interval has expired, then:

starting a subsequent time interval as the current time interval; and

applying the access to the memory system.

11. The method of claim 10 , wherein if the current time interval has not expired then incrementing an access counter.

12. The method of claim 9 , wherein the access rate is equal to a number of accesses per a current time interval.

13. The method of claim 9 , wherein selecting the memory access rate includes selecting a length for the current time interval.

14. The method of claim 13 , wherein the length for the current time interval is less than a regulation time constant of a power supply of the computer system.

15. The method of claim 13 , wherein the length for the current time interval is equal to about 10 microseconds.

16. The method of claim 9 , wherein the desired memory power consumption rate is equal to about 66 percent of a maximum power consumption of each memory module in the memory system.

17. The method of claim 9 , wherein the desired memory power consumption rate is equal to about 9 watts per memory module in the memory system.

18. The method of claim 9 , wherein a DRAM controller controls access to the memory system.