Semiconductor device with semiconductor layer having various thickness
View Patent ↗An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to reach the buried oxide film, so parasitic capacitance is reduced. This structure achieves an SOIMOS transistor capable of reducing junction capacitance at low drain voltage.
1. A semiconductor device comprising:
an insulating layer;
a semiconductor layer of a first conductivity type provided on said insulating layer;
first and second impurity layers of a second conductivity type opposed to said first conductivity type, which are provided apart from each other in an upper region of said semiconductor layer to be kept from contact with said insulating layer;
an electrode opposed to a portion of said upper surface of said semiconductor layer which is sandwiched between said first and second impurity layers, with an insulation film in between; and
a metal compound layer provided on an upper surface of said first impurity layer, said metal compound layer having a first two-dimensional surface along and facing and contacting said upper surface of said first impurity layer and a second two-dimensional surface opposite to the first two-dimensional surface, wherein the second two-dimensional surface is the topmost surface of the metal compound layer and the second two-dimensional surface is below an upper surface of the electrode, wherein
a distance, from said first two-dimensional surface of said metal compound layer, to said insulating layer, is smaller than a thickness of said semiconductor layer between said insulation film and said insulating layer, and
wherein a total thickness of said semiconductor layer and said first impurity layer and said metal compound layer, in a portion of said semiconductor device corresponding to said first impurity layer, is smaller than the thickness of said semiconductor layer between said insulation film and said insulating layer.
2. The semiconductor device according to claim 1 , wherein
said first impurity layer comprises silicon;
said metal compound layer is a compound of cobalt with silicon; and
a thickness of said first impurity layer ranges from 15 to 40 nm.