Apparatus and method for receiving and transmitting serial data
View Patent ↗A serial data communication machine includes a counter for counting a reference clock and a shift register for receiving incoming and outgoing data. Every time the counter counts the reference clock certain times, which is equal to a first integer determined in accordance with a ratio of a reference clock frequency to a transfer rate, the data stored in the shift register are shifted such that the data are transmitted and received at a rate substantially equal to the transfer rate. The communication machine also includes a clock correction unit. Every time the reference clock is generated certain times, which is equal to a second integer determined in accordance with a difference between the above mentioned ratio and the first integer, the clock correction unit temporarily hinders passage of the reference clock to the counter. Even if one bit time is not a multiple of the reference clock, the communication machine can transfer the data at high speed without increasing the reference clock frequency.
1. An apparatus for transmitting and receiving serial data comprising:
a counter for counting a reference clock; and
a shift register for storing incoming or outgoing data, wherein every time the counter counts the reference clock a first number of times, which is equal to a first integer determined in accordance with a ratio of a frequency of the reference clock to a data transfer rate, the incoming or outgoing data stored in the shift register are shifted such that the incoming or outgoing data are received or transmitted at a rate substantially equal to the data transfer rate,
the improvement comprising a clock correction unit for temporarily hindering the reference clock from being passed to the counter every time the reference clock is generated a second number of times, which is equal to a second integer determined in accordance with a difference between the ratio and the first integer.
2. The apparatus according to claim 1 , wherein the apparatus is a universal asynchronous receiver transmitter.
3. The apparatus according to claim 1 , wherein the data transfer rate is at least 38.4 kbps.
4. The apparatus according to claim 1 , wherein one bit time is unequal to a multiple of the reference clock.
5. The apparatus according to claim 1 further including a deactivation unit for deactivating the clock correction unit when the data transfer rate is at most 9600 bps.
6. A method of transmitting and receiving serial data comprising the steps of:
A) determining a first integer on the basis of a ratio of a frequency of a reference clock to a data transfer rate; and
B) shifting out a bit train, which defines incoming or outgoing data, every time the reference clock is counted a first number of times equal to the first integer, thereby transmitting or receiving the outgoing or incoming data at a rate substantially equal to the data transfer rate,
the improvement comprising the steps of:
C) determining a second integer in accordance with a difference between the ratio and the first integer after Step A; and
D) temporarily stopping counting the reference clock every time the reference clock is generated a second number of times equal to the second integer during Step B.
7. The method according to claim 6 , wherein the data transfer rate is at least 38.4 kbps.
8. The method according to claim 6 , wherein one bit time is unequal to a multiple of the reference clock.