Power management for spatial power combiners
View Patent ↗The present invention discloses a system for improving power management for spatial power combining systems, such as a quasi optical grid array amplifier. One aspect of the invention includes the provision of a patterned conductor on the surface the semiconductor chip that opposes the surface upon which the active devices are disposed. This metal material can be used to both enhance heat removal from the chip and to provide a new and more efficient DC biasing path (with the use of vias) for the active components on the other (front) surface of the chip. Another aspect of the invention is the introduction of a dielectric superstrate that attaches to the front surface of the chip to provide an alternative or complementary heat removal and/or biasing structure to the conventional substrate that is typically attached to the back side of the chip. Various combinations of the above features are disclosed.
1. An integrated, spatial power-combining system, comprising:
(a) a spatial power-combining chip having
(i) a front surface with a plurality of active devices disposed thereon, and
(ii) a back surface with patterned, electrically-conductive material disposed thereon; and
(b) a thermally-conductive, dielectric substrate having a front surface attached to the back surface of the spatial power-combining chip.
2. The system of claim 1 , wherein the chip further includes vias disposed between the front surface and patterned, electrically-conductive material on the back surface.
3. The system of claim 1 , wherein the front surface of the dielectric substrate includes patterned, electrically-conductive material disposed thereon that is connected to the patterned material on the back surface of the power-combining chip.
4. The system of claim 3 , wherein the patterned, electrically-conductive material on the back surface of the power-combining chip is connected to the patterned, electrically-conductive material on the front surface of the substrate with one of a solder bond, a thermo-compression bond, an ultrasonic bond and an electrically-conductive adhesive.
5. The system of claim 1 , further including
(c) a thermally-conductive, dielectric superstrate having a back surface joined to the front surface of the spatial power-combining chip.
6. The system of claim 5 , wherein the back surface of the dielectric superstrate is joined to the front surface of the power-combining structure via a thermally-conductive dielectric joint disposed therebetween.
7. The system of claim 5 , wherein the back surface of the dielectric superstrate includes patterned, electrically-conductive material disposed thereon that is joined to the front surface of the power-combining structure.
8. The system of claim 7 , wherein the front surface of the chip further includes patterned, electrically-conductive material.
9. The system of claim 8 , further including
vias disposed within the spatial power-combining structure and between the patterns on the front and back surfaces of the structure that provides an electrical path for DC power to the front surface of the chip, and wherein
the patterned, electrically-conductive material disposed on the front surface of the substrate is joined to the patterned, electrically-conductive material disposed on the back surface of the power-combining structure via an electrically-conducting joint, and
the patterned, electrically-conductive material disposed on the back surface of the superstrate is joined to the patterned, electrically-conductive material disposed on the front surface of the power-combining structure via an electrically-conducting joint.
10. The system of claim 1 , wherein the plurality of active devices comprise a quasi-optical grid array.
11. An integrated spatial power-combining system, comprising:
(a) a spatial power-combining chip having front and back surfaces and active devices integrated on the front surface; and
(b) a thermally-conductive, dielectric superstrate having a back surface attached to the front surface of the spatial power-combining chip,
wherein the back surface of the dielectric superstrate includes patterned, electrically-conductive material disposed thereon that is connected to the front surface of the power-combining chip.
12. The system of claim 11 , wherein the front surface of the chip further includes patterned, electrically-conductive material that is connected to the patterned, electrically-conductive material on the back surface of the superstrate with one of a solder bond, a thermo-compression bond, an ultrasonic bond and an electrically-conductive adhesive.
13. The system of claim 12 , further including
(c) a first thermally-conductive joint disposed between the front surface of the power-combining chip and the back surface of the superstrate.
14. The system of claim 13 , further including
(d) a thermally-conductive, dielectric substrate having a front surface attached to the back surface of the chip.
15. The system of claim 14 , further including
a thermally-conductive joint disposed between the back surface of the power-combining chip the front surface of the substrate.
16. A method of drawing heat away from a spatial power-combining chip having a front surface with heat-generating, active components disposed thereon and a back surface that is connected to a thermally-conducting substrate, comprising:
(a) providing a metal pattern on the back surface of the chip;
(b) providing a metal pattern on the front surface of the substrate; and
(c) joining the metal pattern on the back surface of the chip to the metal pattern on the front surface of the substrate in order to draw heat generated by the active devices away from the chip.
17. A method of drawing heat away from a spatial power-combining chip having a front surface with a plurality of heat-generating active devices disposed thereon, comprising:
(a) providing a thermally-conducting dielectric superstrate having front and back surfaces; and
(b) attaching the front surface of the power-combining chip to the back surface of the superstrate via a thermally-conducting joint.
18. The method of claim 17 , wherein the back surface of the thermally-conducting dielectric superstrate includes a metal pattern disposed thereon, and wherein the attaching includes joining the metal pattern disposed on the back surface of the superstrate with the front surface of the chip.
19. The method of claim 18 , wherein the front surface of the chip further includes a metal pattern disposed thereon and the metal pattern on the back surface of the superstrate is joined to the metal pattern on the front surface of the chip.
20. A method of providing DC power to active components on a power-combining chip having front and back surfaces, wherein the components are disposed on the front surface of the chip, comprising:
(a) providing a metal pattern on the back surface of the power-combining chip;
(b) selectively connecting one or more of the active components to the metal pattern on the back surface of the chip;
(c) providing DC power to the metal pattern on the back surface of the chip;
(d) providing a thermally-conducting, dielectric substrate having a front surface with a metal pattern disposed thereon;
(e) electrically connecting the metal pattern on the front surface of the dielectric substrate to the metal pattern on the back surface of the power-combining chip; and
(f) supplying DC power to the metal pattern on the front surface of the dielectric substrate.
21. The method of claim 20 , wherein one or more of the active components are selectively connected to the metal pattern on the back surface of the chip with vias disposed between the front and back surfaces of the power-combining chip.
22. A method of providing DC power to active components on a power-combining chip having front and back surfaces, wherein the components are disposed on the front surface of the chip, comprising:
(a) providing a thermally-conducting dielectric superstrate having a back surface with a metal pattern disposed thereon;
(b) electrically connecting the metal pattern on the back surface of the superstrate to selected components on the front surface of the chip; and
(c) applying DC power to the metal pattern on the back surface of the superstrate.